standard cell library
**Standard cell** is the pre-designed, pre-characterized logic building block that every digital chip is assembled from — a fixed-height rectangle containing a handful of transistors that implements one Boolean function (NAND, NOR, INV, AOI, MUX, flip-flop, latch, buffer). A foundry PDK ships a library of 500–2000 standard cells spanning multiple drive strengths, threshold voltages, and functions; the synthesis tool maps RTL into these cells, and place-and-route tiles them edge-to-edge in rows across the die. An Apple M-series chip contains billions of transistors, but they are organized into perhaps 50–100 million placed standard-cell instances drawn from a library of ~1000 unique cells.
**Anatomy of a standard cell.** Every cell in a row-based library shares the same height (measured in metal-pitch "tracks") and a width that is an integer multiple of the placement grid (contacted poly pitch, CPP). Within the fixed height:
- **N-well band** occupies the upper portion — PMOS transistors live here.
- **P-substrate band** occupies the lower portion — NMOS transistors live here.
- **VDD rail** runs along the top edge; **VSS rail** along the bottom — power is continuous across the row.
- **Pin access** is on lower metal layers (M1, M2) at predefined grid positions so the router can connect cells.
- **Abutment edges** match between adjacent cells — shared well taps and continuous power rails, zero wasted space.
$$\text{Cell height} = N_{\text{tracks}} \times M2_{\text{pitch}}$$
At TSMC N5 with 28 nm M2 pitch and a 6.5-track (6.5T) cell library: height = 6.5 × 28 = **182 nm**. At 2 nm (21 nm pitch, 5T): height = 5 × 21 = **105 nm**.
**Cell height scaling — the dominant density knob.** Reducing cell height (from 9T → 7.5T → 6T → 5T → 4T) is the primary way to shrink standard-cell area across nodes, more impactful than transistor pitch scaling alone:
| Node | CPP (nm) | M2 pitch (nm) | Typical cell height | Tracks | Cell area trend |
|---|---|---|---|---|---|
| 7 nm (N7) | 54 | 36 | 7.5T = 270 nm | 7.5 | 1.0× (baseline) |
| 5 nm (N5) | 48 | 28 | 6.5T = 182 nm | 6.5 | ~0.67× |
| 3 nm (N3) | 48 | 23 | 6T = 138 nm | 6 | ~0.51× |
| 2 nm (N2, GAA) | 45 | 21 | 5T = 105 nm | 5 | ~0.39× |
| 14A (BSPDN) | 42 | 18 | 4.5T = 81 nm | 4.5 | ~0.30× |
Fewer tracks means fewer routing resources inside the cell, making internal wiring harder. Below 5T, **backside power delivery (BSPDN)** removes the VDD/VSS rails from the cell interior, recovering 1–2 tracks for signal routing — which is why BSPDN and ultra-short cells are co-adopted at the 2 nm node.
**Drive strength and Vt variants.** Each logic function (e.g. NAND2) is implemented in multiple variants:
- **Drive strengths** (X1, X2, X4, X8…): wider transistors for faster output transitions at the cost of more area and leakage. Synthesis picks the minimum strength that meets timing.
- **Threshold-voltage flavors** (SVT, LVT, ULVT, HVT): lower Vt → faster switching but exponentially more leakage. A typical chip uses 60% SVT, 25% LVT, 10% HVT, 5% ULVT — mixing them to meet both speed and power targets.
- **Channel length variants** (for leakage-critical paths): longer Lgate reduces DIBL and leakage at the cost of drive current.
A full N5 library might contain: 200 functions × 6 drive strengths × 4 Vt options = **~4800 cell variants**, each independently characterized for timing, power, and noise.
**Liberty (.lib) characterization.** Every cell is characterized by SPICE simulation across PVT (process, voltage, temperature) corners into a Liberty timing model:
- **Delay** (cell rise/fall) as a function of input slew × output load — stored as a 2D lookup table (NLDM) or as current-source waveforms (CCS/ECSM).
- **Transition time** (output slew) — same 2D table.
- **Setup/hold** for sequential cells — constraint tables indexed by data slew × clock slew.
- **Leakage power** per input state.
- **Dynamic power** — internal energy per transition + switching energy ($C_{\text{load}} \cdot V_{\text{DD}}^2$).
The synthesis and STA tools never run SPICE — they interpolate these pre-computed tables millions of times per second to evaluate billions of paths.
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**The synthesis-to-layout flow.** Standard cells are the interface between logic design and physical implementation: (1) **Synthesis** (Genus, DC) maps RTL into a gate-level netlist of library cells; (2) **Placement** (Innovus, ICC2) assigns each cell instance to a row position minimizing wirelength and congestion; (3) **Clock-tree synthesis** inserts buffer/inverter cells to distribute the clock with minimal skew; (4) **Routing** connects cell pins through the metal stack; (5) **Timing optimization** swaps cells to stronger/weaker drive or different Vt to fix setup/hold violations. The quality of the standard-cell library — its density, speed, and completeness — directly determines the PPA (performance, power, area) a design can achieve at a given node.
**What this means for AI accelerators.** A modern GPU or TPU die at 3–5 nm contains 50–100 billion transistors organized as tens of millions of placed cells. The cell library's area efficiency (track height, CPP, pin-access rules) determines how many compute units (tensor cores, systolic array PEs) physically fit on the die — which directly gates TOPS and training throughput. Every node's headline "transistor density" (MTr/mm²) is primarily a function of standard-cell height × CPP, not the transistor itself. The CFS platform simulates the transistor physics at /transistor and the array-level compute at /systolic — the standard cell is the bridge between them.