Subthreshold Leakage

Subthreshold leakage is the current that flows through a transistor even when it's supposed to be fully off — gate voltage below the threshold voltage, in principle zero current, but real MOSFETs leak exponentially rather than switching off cleanly. Every transistor on a chip leaks some amount of this current continuously, all the time, whether it's actively switching or just sitting idle holding a logic state, which is exactly why subthreshold leakage became one of the central problems in chip design once transistor counts climbed into the billions. At a high level, the leakage problem and its relationship to scaling looks like this:

The reason leakage current scales exponentially, not linearly, with threshold voltage is the specific mathematical trap that makes this problem so hard to escape. Subthreshold current follows roughly I ∝ exp(-Vt/S), where S is the subthreshold swing (how many millivolts of gate voltage change it takes to change drain current by 10x) — at room temperature, the best a classical MOSFET can achieve is about 60 millivolts per decade, meaning every 60mV you lower the threshold voltage to speed the transistor up, leakage current goes up by a full 10x. This is why "just lower Vt for more speed" stopped being a free lever once leakage became a meaningful fraction of total chip power: the speed-leakage tradeoff is baked into the physics, not an engineering oversight.

Billions of leaking transistors add up to a real, measurable fraction of a modern chip's total power budget, which is why leakage stopped being a rounding error once process nodes shrank past roughly 90nm. At older, larger nodes, leakage per transistor was negligible relative to switching (dynamic) power; as transistor counts climbed into the tens of billions and node sizes shrank, aggregate static leakage power became comparable to, and in some idle-heavy workloads larger than, the active switching power — a real design constraint that shows up directly in battery life for mobile chips and cooling requirements for data-center GPUs that are never fully idle.

Multiple mitigations exist because no single fix solves the underlying physics, so modern chips stack several leakage-control techniques simultaneously. Multiple threshold voltages on the same chip (high-Vt transistors for non-critical paths that can tolerate being slower but leakier-free, low-Vt transistors only on the critical timing path) trade some design complexity for real power savings; power gating physically disconnects unused blocks from the supply rail entirely rather than just turning transistors off logically; FinFET and now gate-all-around transistor structures wrap the gate around the channel on multiple sides instead of one, giving far tighter electrostatic control over the channel and a steeper (better) subthreshold slope than a classical planar MOSFET can achieve — this structural change, not a materials trick, is the real reason FinFET-based nodes could keep scaling Vt down without leakage exploding the way it would have on planar transistors.

Read subthreshold leakage as the physics bill that comes due the moment a chip has enough transistors for "small inefficiency per device" to become "measurable fraction of total power": the 60mV/decade relationship between threshold voltage and leakage is a hard limit on classical planar CMOS, and the entire arc of FinFET and gate-all-around adoption is best understood as the industry buying back some of that margin through better channel geometry, not through any change to the underlying silicon physics itself.