teos

**TEOS-Based Silicon Dioxide Deposition** is the **use of tetraethyl orthosilicate (Si(OC₂H₅)₄) as a precursor gas for low-pressure CVD (LPCVD) or plasma-enhanced CVD (PECVD) oxide deposition — enabling conformal, high-quality SiO₂ films for interlayer dielectrics, spacers, and gap fill across all CMOS generations**. TEOS is the dominant oxide source gas in semiconductor manufacturing. **LPCVD TEOS Process** LPCVD TEOS operates at 680-750°C and ~0.5-2 torr pressure, where TEOS vapor decomposes via thermal pyrolysis: TEOS + O₂ → SiO₂ + byproducts. The pyrolysis reaction is temperature-limited and surface-limited (not diffusion-limited), enabling conformal deposition on high-aspect-ratio features (AR > 5:1). Deposition rate is ~50-200 nm/min depending on temperature and pressure. Deposited oxide has good density (>99% theoretical) and low impurity content (N, C < 1 wt%). **PECVD TEOS Process** For lower temperature processing (400-500°C), plasma-enhanced CVD (PECVD) TEOS is used. Plasma excitation (RF, 13.56 MHz) activates TEOS decomposition at lower temperatures, enabling integration with temperature-sensitive materials (polymers, low-Tg dielectrics) and shallow junction preservation. PECVD film density is slightly lower (~95% theoretical) and hydrogen content is higher (SiOₓHᵧ) compared to LPCVD, but conformality is excellent. **O₃-TEOS SACVD Gap Fill** For aggressive gap-fill applications, O₃-TEOS SACVD (sub-atmospheric CVD with ozone) combines ozone as oxidizer with TEOS. Ozone reaction path (TEOS + O₃) is surface-reaction-limited rather than diffusion-limited, enabling superior gap fill without pinholes at high aspect ratio (6:1 to 8:1). The surface-reaction-limited regime ensures that decomposition occurs only at exposed surfaces, preventing void formation deep in trenches. O₃-TEOS is standard for pre-metal dielectric (PMD) and has enabled aggressive interconnect scaling. **Reflow Characteristics** TEOS oxide can be reflowed at elevated temperature (~900-1000°C) to smooth surface topography and heal small pinholes. Reflow is used after spacer deposition (to smooth spacer sidewalls for better gate dielectric coverage) or after PMD deposition (to planarize before metal). However, reflow increases dopant diffusion and can damage shallow junctions; modern processes minimize reflow in favor of CMP planarization. **TEOS Oxide Etch Rate and Selectivity** TEOS oxide has lower etch rate in HF (~1 nm/min in 6:1 BOE) compared to other CVD oxides, due to higher density and lower impurity content. This slower etch rate requires longer etch times but provides better selectivity to silicon and silicon nitride. HF-last cleaning (HF + H₂O₂ + H₂O) selectively etches native oxide on contact surfaces while leaving TEOS oxide largely intact. TEOS selectivity to spacer (SiN) is typically >1:10 (SiO₂:SiN etch rate ratio), enabling thick spacers without over-etching oxide. **TEOS Contamination and Gettering** Pure TEOS is a clean precursor with minimal metal impurity. However, it can decompose to leave carbon residue (forming SiOₓCᵧ) if temperature is too low or residence time too long. Carbon contamination increases etch rate and reduces oxide quality. To mitigate, ultra-pure TEOS sources and strict temperature control are used. Some processes dope TEOS oxide with phosphorus (by adding phosphine PH₃) to create PSG for gettering mobile ions. **Interface Quality and Defect Density** TEOS-based oxides achieve low interface trap density (Dit ~ 10⁹-10¹⁰ cm⁻² eV⁻¹) when deposited conformal and annealed properly. The Si/SiO₂ interface quality determines charge trapping behavior and reliability (PBTI/NBTI). Post-deposition annealing in N₂ or forming gas (H₂/N₂) at 400-500°C improves interface quality via hydrogen passivation. **Applications Across CMOS** TEOS is ubiquitous: spacer oxides (after SiN spacer etch), PMD gap fill (SACVD), first-level dielectric between metal lines, and shallow trench isolation (STI) fill. Its versatility stems from excellent gap fill, ease of control, and reliability. Newer high-k and low-k materials often use TEOS or TEOS-based chemistries as interlayers. **Summary** TEOS-based oxide deposition is a cornerstone of CMOS manufacturing, providing conformal, reliable SiO₂ films across diverse applications. Continued optimization in CVD chemistry, gap fill, and etch selectivity will support interconnect scaling for generations to come.