thermal oxidation
Thermal oxidation converts the exposed surface of a silicon wafer into silicon dioxide by reacting silicon with dry oxygen or steam at elevated temperature. Unlike deposited oxide, the film grows by consuming the substrate, so the process creates a dense dielectric and an exceptionally well controlled silicon–silicon dioxide interface. That interface enabled the planar MOS process and remains important even where high-k gate stacks have replaced bulk silicon dioxide as the primary gate dielectric.
**Dry oxygen and steam perform the same net conversion but occupy different process windows.** Dry oxidation follows Si + O₂ → SiO₂ and is comparatively slow, which improves thickness control and is preferred when interface quality, electrical integrity, or a thin film matters more than throughput. Wet oxidation follows Si + 2H₂O → SiO₂ + 2H₂ and grows much faster because water has greater solubility and diffusivity in silicon dioxide; it is therefore useful for thick field, masking, or sacrificial oxides. Production furnaces commonly operate within roughly 800–1200°C, but the selected temperature, pressure, oxidant purity, wafer orientation, doping, chlorine chemistry, and thermal budget determine the actual rate and film properties. A process engineer does not substitute wet time for dry time by a simple constant factor because the two ambients have different kinetic constants and produce films with different electrical and structural behavior.
**Oxide growth has three serial transport steps and whichever step is slowest controls the observed kinetics.** Oxidant first moves from the bulk gas through a boundary layer to the oxide surface, then dissolves into and diffuses through the oxide already present, and finally reacts with silicon at the buried interface. For a well-designed furnace the gas-phase delivery resistance is small enough that diffusion through the film and interface reaction dominate. A thin film presents a short diffusion path, so reaction at the interface controls growth; as the film thickens, the oxidant must travel farther and diffusion becomes controlling. The interface moves into the wafer because new oxide forms at the silicon boundary rather than being added only at the outer surface. Volume expansion means that growing 1.00 nm of SiO₂ consumes approximately 0.44 nm of silicon and leaves about 0.56 nm above the original silicon surface, a geometric fact that matters at isolation edges and patterned topography.
**The Deal–Grove model turns those physical steps into a practical time-to-thickness equation.** For oxide thickness $x$, oxidation time $t$, linear rate constant $B/A$, parabolic rate constant $B$, and time shift $\tau$ representing initial oxide, the planar model is
$$
x^2 + Ax = B(t+\tau), \qquad
x(t)=\frac{A}{2}\left[\sqrt{1+\frac{4B(t+\tau)}{A^2}}-1\right].
$$
When $x \ll A$, the relationship approaches $x \approx (B/A)(t+\tau)$ and interface reaction is the main resistance. When $x \gg A$, it approaches $x^2 \approx B(t+\tau)$ and diffusion through the existing oxide controls the rate. Both constants are strongly temperature dependent and are normally represented by Arrhenius laws, $B=B_0\exp(-E_B/kT)$ and $B/A=(B/A)_0\exp(-E_L/kT)$. Calibration therefore requires measured rate constants for the specific furnace, ambient, pressure, crystal orientation, and wafer condition rather than a universal textbook curve. Very thin oxides can grow faster than the classical model predicts, so modern ultrathin recipes use empirical extensions or reaction-network models rather than extrapolating Deal–Grove to zero thickness.
| Process choice | Relative growth rate | Typical reason to choose it | Principal control concern |
|---|---:|---|---|
| Dry O₂ | Slow | Thin electrical oxide, liner, or final quality step | Time resolution, interface charge, leakage |
| Steam or pyrogenic H₂O | Fast | Thick field, masking, or sacrificial oxide | Uniformity, hydrogen-related defects, densification |
| Dry–wet–dry sequence | Moderate to fast | Thick film with controlled interfaces and finish | Ambient transition and total thermal budget |
| Chlorinated dry oxidation | Slow | Cleaner interface and improved mobile-ion control | Chlorine dose, corrosion, exhaust safety |
| Rapid thermal oxidation | Very fast thermal cycle | Thin oxide with reduced dopant diffusion | Temperature calibration and wafer-edge uniformity |
**A manufacturable recipe controls the wafer before, during, and after the nominal oxidation interval.** Native oxide, organic residue, particles, metallic contamination, and surface termination change nucleation and interface states, so preclean and queue time are part of the electrical process rather than housekeeping details. Wafers enter a quartz tube or rapid thermal chamber, stabilize under an inert purge, ramp to temperature, receive a controlled oxidant flow, and then exit or cool without an uncontrolled reoxidation step. Pyrogenic steam may be generated by burning high-purity hydrogen and oxygen; a bubbler or direct-steam source can also be used when its contamination and flow behavior are qualified. Temperature gradients, furnace loading, wafer spacing, gas depletion, and boat position all appear as within-wafer or wafer-to-wafer thickness signatures. Ellipsometry or reflectometry maps thickness and refractive index, while electrical monitor structures measure breakdown, charge, leakage, and interface behavior that optical thickness alone cannot reveal.
```flowchart
Define target thickness and electrical function → Select dry, wet, mixed, or rapid-thermal ambient → Preclean and control queue time → Load and inert purge → Stabilize temperature and pressure → Admit oxidant for modeled time → Inert purge and controlled cooldown → Map thickness and refractive index → Measure electrical monitors → Feed rate and uniformity corrections back to the recipe
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**Crystal orientation, dopants, pressure, and stress make real wafers depart systematically from an ideal planar calibration.** The Si(111) surface generally oxidizes faster than Si(100) under comparable conditions because its interfacial reaction density differs. Heavy boron or phosphorus doping can enhance oxidation, especially when segregation and point-defect populations alter the interface chemistry, while some dopant profiles move during the high-temperature cycle and change the intended junction. Higher oxidant pressure increases surface concentration and can accelerate growth, enabling pressure oxidation where thermal budget or throughput justifies more complex equipment. Pattern corners develop stress because silicon expands as it becomes oxide; compressive stress can retard local growth and generate nonuniform shapes near nitride masks. The same oxidation also injects silicon self-interstitials, coupling oxide growth to transient-enhanced dopant diffusion. Process simulation must therefore solve geometry, oxidation, stress, and diffusion together when a few nanometers of encroachment changes device behavior.
**Patterned oxidation creates isolation features but also exposes the mechanical consequences of volume expansion.** In local oxidation of silicon, a silicon nitride mask blocks oxidant while a pad oxide reduces nitride-induced stress. Oxidant diffuses laterally beneath the mask edge and forms the characteristic bird’s-beak encroachment, consuming active area and limiting scaling. Shallow trench isolation replaced LOCOS for dense logic because etched trenches give tighter lateral control, yet thermal liner oxidation is still used to heal etch damage, round corners, and improve the silicon interface before dielectric fill. Sacrificial oxidation deliberately consumes a thin damaged silicon layer and is then stripped, leaving a cleaner surface for the next module. Oxide can also serve as an implant or diffusion mask, a hard mask, a passivation layer, and part of silicon-on-insulator or power-device structures; each use assigns a different optimum to growth rate, stress, density, and interface quality.
**Electrical quality is judged at the interface and across the film, not from thickness alone.** Thermally grown SiO₂ has a relative dielectric constant near 3.9 and a high-quality film can exhibit breakdown fields on the order of 10 MV/cm, but those headline values do not guarantee a production-worthy gate dielectric. Fixed oxide charge shifts threshold voltage, interface traps degrade subthreshold behavior and mobility, mobile ions cause bias-temperature drift, and traps inside the oxide support stress-induced leakage and time-dependent dielectric breakdown. Capacitance–voltage structures extract oxide capacitance, flat-band voltage, hysteresis, and interface-trap behavior; current–voltage ramps screen leakage and breakdown; charge-to-breakdown and constant-voltage stress compare reliability across splits. Chlorine-bearing ambients have historically helped getter mobile sodium and improve cleanliness, while forming-gas anneals passivate many dangling bonds with hydrogen. Anneal benefits must be balanced against hydrogen stability, dopant movement, and the thermal budget of every completed device layer.
**Thermal oxidation remains relevant even though advanced logic no longer uses thick pure SiO₂ as its complete gate dielectric.** As SiO₂ became only a few atomic layers thick, direct tunneling current rose too sharply for continued equivalent-oxide-thickness scaling. High-k dielectrics such as HfO₂ provide larger physical thickness at comparable capacitance, but an ultrathin silicon oxide or silicon oxynitride interfacial layer is often retained because the silicon interface strongly affects mobility, threshold stability, and reliability. The distinction between physical thickness and electrical thickness is expressed through equivalent oxide thickness,
$$
\mathrm{EOT}=t_{\mathrm{high-k}}\frac{3.9}{\kappa_{\mathrm{high-k}}}+t_{\mathrm{IL}},
$$
where $t_{\mathrm{IL}}$ is the SiO₂-equivalent contribution of the interfacial layer. This is why a sub-nanometer change in an interfacial oxidation step can move device capacitance and threshold even when the deposited high-k thickness is unchanged. Thermal oxide also persists in mature-node CMOS, analog, MEMS, photonics, sensors, isolation liners, sacrificial cleans, and power devices, where its interface and process maturity outweigh the pressure for minimum EOT.
The most useful process-control view is to treat thermal oxidation as a moving-boundary reaction whose output is simultaneously geometry, material, interface, and thermal history. A furnace may hit mean thickness while failing edge uniformity, mobile-ion control, interface-trap density, stress, or downstream junction placement; conversely, a slower dry recipe may be economically superior when it reduces electrical fallout. Read thermal oxidation through a transport-and-interface lens: oxidant delivery sets the available reactant, diffusion through existing SiO₂ creates the thickness dependence, interface chemistry determines thin-film kinetics and electrical quality, and silicon consumption couples the oxide recipe to every structure beneath and beside it.