thermal sensor design on chip

**Thermal Sensor and Management Circuits** are **on-chip temperature measurement and control systems that monitor junction temperature at multiple die locations and trigger throttling, voltage scaling, or emergency shutdown to prevent thermal damage and ensure reliable operation within specification**. **BJT-Based Temperature Sensors:** - **Principle**: forward voltage (VBE) of a BJT decreases linearly with temperature (~-1.8 mV/°C) — measuring voltage difference between two BJTs biased at different current densities (ΔVBE) provides PTAT (proportional to absolute temperature) voltage - **Sigma-Delta Readout**: ΔVBE and VBE are digitized using a sigma-delta ADC integrated with the sensor — achieves ±0.5°C accuracy after one-point calibration with 12-16 bit resolution - **Calibration**: wafer-level trimming corrects for process variation in BJT parameters — single-point trim at room temperature combined with curvature correction achieves ±1°C accuracy across -40°C to 125°C - **Layout**: substrate PNP transistors in isolated wells minimize noise coupling from digital circuits — guard rings and deep N-well isolation improve measurement accuracy in noisy SoC environments **Ring Oscillator Temperature Sensors:** - **Principle**: inverter delay increases with temperature (mobility degradation) — ring oscillator frequency decreases approximately linearly with temperature, easily digitized by counting oscillator periods - **Advantages**: fully digital implementation, no analog circuitry required, easily synthesized and placed anywhere in the design — ideal for distributed thermal monitoring with 10-50 sensors across a large die - **Resolution**: frequency counting over 10-100 μs measurement windows achieves ±1-3°C resolution — faster measurement trades accuracy for response time - **Area**: < 500 μm² per sensor in advanced nodes — negligible overhead enables fine-grained thermal mapping across CPU cores, GPU clusters, and memory arrays **Dynamic Thermal Management (DTM):** - **Threshold-Based Control**: PMU monitors all thermal sensors and applies multi-level throttling — warning threshold triggers DVFS reduction, critical threshold reduces clock frequency, emergency threshold initiates thermal shutdown - **DVFS Integration**: thermal controller requests lower voltage/frequency operating point from clock/power management — response latency of 1-10 μs prevents thermal runaway during burst workloads - **Per-Core Throttling**: independent thermal management per CPU core or functional block allows hot cores to throttle while cool cores continue at full performance — improves total throughput compared to chip-wide throttling - **Thermal Prediction**: temperature rise rate extrapolation predicts future thermal violations — proactive throttling can begin before threshold is reached, reducing performance impact **On-chip thermal sensing and management is a mandatory reliability feature in all modern processors — without DTM, localized hotspots from concentrated switching activity would exceed the maximum junction temperature specification of 105-125°C within milliseconds during peak workloads.**