threshold voltage tuning

```svg ``` **Threshold Voltage Tuning** is the **engineering of $V_t$ to meet the performance and power targets of each transistor type on a chip** — achieved through a combination of channel doping, gate work function metal selection, interface dipoles, and body biasing. **How Is $V_t$ Tuned?** - **Channel Doping**: Higher NA (P-type) increases $V_t$ for NMOS. Used in planar bulk CMOS. - **Work Function Metal**: Different metal stacks (TiN/TiAl) shift $Phi_m$ -> shift $V_t$. Primary method in HKMG. - **Interface Dipoles**: La₂O₃ or Al₂O₃ interlayers at the IL/high-k interface create fixed dipoles that shift $V_t$. - **Body Biasing**: In FD-SOI, back-gate voltage shifts $V_t$ dynamically (±300 mV). **Why It Matters** - **Multi-$V_t$ Library**: Modern SoCs use 4-8 $V_t$ variants (uLVT, LVT, SVT, HVT, uHVT) for optimal power-performance trade-offs. - **Each $V_t$**: Lower $V_t$ = faster but leakier. Higher $V_t$ = slower but lower leakage. - **Design Choice**: Performance-critical paths use LVT; always-on logic uses HVT. **Threshold Voltage Tuning** is **the power-performance dial for every transistor** — providing designers with multiple performance grades to optimize each circuit block.