timing closure methodology mcmm
**Timing Closure Methodology (MCMM)** is the **iterative process of achieving timing sign-off across all operating conditions (corners) and functional modes simultaneously**, using Multi-Corner Multi-Mode (MCMM) analysis that captures the full space of process, voltage, temperature (PVT) variations and functional configurations that the chip must support.
Timing closure is often the most time-consuming and iteration-intensive phase of physical implementation. A design that fails timing at any PVT corner in any operating mode will not function reliably in the field.
**MCMM Analysis Space**:
| Dimension | Variations | Purpose |
|-----------|-----------|----------|
| **Process corners** | SS, TT, FF, SF, FS | Manufacturing variation |
| **Voltage** | 0.675V, 0.75V, 0.825V | Supply variation |
| **Temperature** | -40C, 25C, 125C | Operating range |
| **Modes** | Functional, scan, JTAG, MBIST | Operating configurations |
| **OCV/AOCV** | On-chip variation derating | Local variation |
**Corner Selection**: The full PVT cross-product can produce 50-100+ analysis scenarios. The worst-case corners are: **setup** — slow process, low voltage, high temperature (SS/0.675V/125C) where gates are slowest; **hold** — fast process, high voltage, low temperature (FF/0.825V/-40C) where gates are fastest (hold violations occur when data arrives too early).
**On-Chip Variation (OCV)**: Even within a single die, transistors and wires vary due to local process variation. **OCV derating** applies pessimistic multipliers to launch and capture paths: for setup, launch path gets early (slow) derate and capture path gets late (fast) derate. **AOCV (Advanced OCV)** provides path-depth-dependent derating — longer paths have less variation (statistical averaging) than short paths. **POCV/LVF (Parametric OCV/Liberty Variation Format)** provides the most accurate statistical derating using per-cell variation data.
**Hold Closure**: Hold violations are more dangerous than setup violations because they cannot be fixed by reducing clock frequency. Hold fixing inserts delay buffers in short paths to ensure data doesn't arrive too early at the capture flip-flop. This is typically done automatically by the P&R tool, but the buffer insertion can impact setup timing and routing congestion — requiring iterative optimization.
**Timing Closure Flow**:
1. **Initial synthesis** with timing constraints (SDC)
2. **Placement** with timing-driven optimization
3. **Clock tree synthesis (CTS)** — balance clock skew
4. **Post-CTS optimization** — fix setup violations with sizing, buffering
5. **Routing** — extract parasitics from actual wire geometries
6. **Post-route optimization** — fix timing with real parasitics
7. **Signoff STA** — final timing analysis with signoff-quality extraction and AOCV
8. **ECO (Engineering Change Order)** — targeted fixes for remaining violations
**Common Bottlenecks**: **Clock skew** (large skew between launch and capture clocks consumes timing margin — CTS must balance carefully); **long interconnect** (cross-chip wires dominate delay at advanced nodes — repeater insertion and floorplan optimization); **congestion** (detour routing increases wire length and delay); and **multi-cycle paths / false paths** (incorrect SDC constraints cause tools to over-optimize non-critical paths).
**Timing closure methodology is the ultimate integration challenge in chip design — it simultaneously satisfies thousands of constraints across dozens of operating conditions, requiring the synthesis of timing analysis, physical optimization, and engineering judgment into a convergent iterative process.**