tolerance

**Tolerance** in semiconductor manufacturing is the **allowable range of variation for a measured parameter** — defined as the difference between the upper and lower specification limits: $Tolerance = USL - LSL$, specifying how much deviation from the target value is acceptable. **Tolerance Context** - **CD Tolerance**: For a 20nm target gate CD with ±2nm tolerance — USL = 22nm, LSL = 18nm, tolerance = 4nm. - **Overlay Tolerance**: Overlay specification of ±1.5nm — total tolerance = 3nm. - **Symmetric**: $Tolerance = 2 imes deviation$ when specs are symmetric around target. - **Asymmetric**: USL - target ≠ target - LSL — different allowances above and below target. **Why It Matters** - **Shrinking**: Tolerances tighten with each technology node — <3nm node tolerances are sub-nanometer for critical parameters. - **Capability**: $Cp = frac{Tolerance}{6sigma}$ — tolerance and process variation together determine capability. - **Stackup**: Tolerance stackup (RSS combination of individual tolerances) determines system-level variation. **Tolerance** is **the allowable error budget** — the total acceptable range of variation for a parameter, defining how much manufacturing imprecision is acceptable.