Transistor Architecture Naming Planar FinFET GAA
Each transistor generation is named after the literal geometry of its channel, and the names form a direct timeline of how many sides of the channel the gate wraps around. A planar transistor is named for a channel that lies flat on the wafer surface, gated from one side only. A FinFET is named for a channel shaped like a thin vertical fin, gated from three sides as the gate drapes over it. A gate-all-around (GAA) transistor is named for literally surrounding the channel on all sides, and its two common shapes — nanosheet and nanowire — are named for whether that fully-wrapped channel is a wide, flat sheet or a thin, round wire. Reading the name tells you the gate-wrap count before you read a single spec.
A few things explain why the gate-wrap count in the name tracks the real engineering story so closely:
More sides gated means tighter control over the channel, and that control is the entire reason the industry kept adding sides. A planar transistor's single gated side leaves current free to leak along paths the gate cannot influence as the channel shrinks, a problem that worsens every time the channel gets shorter. Wrapping the gate around three sides in a FinFET suppresses most of that leakage by surrounding more of the channel's surface with gate control; wrapping all four sides in a GAA device suppresses it further still, because no face of the channel escapes the gate's electric field. The fin and gate-all-around names are, in effect, leakage-suppression milestones disguised as shape descriptions.
Nanosheet and nanowire are named for a width-versus-current tradeoff, not for an arbitrary manufacturing choice. A nanowire's round, thin cross section gives the tightest possible gate control for its size but carries less current per channel, since current-carrying capacity roughly tracks cross-sectional area; a nanosheet widens that same fully-wrapped geometry into a flatter, broader cross section to carry more current per channel while keeping the same all-around gate coverage. Multiple nanosheets can also be stacked vertically to multiply the current-carrying area within one transistor's footprint, which is why nanosheet, not nanowire, became the industry's practical choice for GAA logic despite nanowire's name appearing first in research literature.
The naming sequence is also a roadmap of which problem each generation was created to solve, in order. Planar's single-side gating was adequate until shrinking gate lengths let leakage current sneak underneath the channel; FinFET's three-side wrap fixed most of that by standing the channel on edge; GAA's fourth side closed the one leakage path FinFET still left open, directly beneath the fin. Nanosheet then answered FinFET's narrower problem — not leakage, but current-carrying area shrinking as fins got thinner — by widening the fully-wrapped channel back out and stacking it.
Siblings worth distinguishing: this entry covers the channel-shape naming logic across transistor generations specifically; it does not cover CMOS-logic-family naming, memory-cell naming (such as 1T1C DRAM), or any single generation's detailed fabrication steps, each a separate, already-covered topic with its own name.
Read a transistor architecture's name as a direct count of gated sides and nothing more exotic: planar means one side, FinFET means three, and gate-all-around means four, with nanosheet and nanowire distinguishing a wide, flat four-sided channel from a thin, round one — the entire multi-decade transistor roadmap compressed into how many faces of a channel the gate is drawn wrapping around.