tungsten plug process
**Tungsten Plug Process** is the **chemical vapor deposition sequence that fills vertical contact holes and vias with tungsten metal to create the electrically conductive vertical connections between transistor terminals and the first metal layer (or between metal layers in BEOL)** — one of the most dimensionally challenging fill processes in CMOS, where aspect ratios of 10:1 to 20:1 must be filled void-free with a material that has a CVD nucleation problem, requiring a carefully sequenced nucleation layer + bulk fill approach.
**Why Tungsten for Contacts**
- High melting point (3422°C) → stable through all subsequent process temperatures.
- Low resistivity (5.6 µΩ·cm bulk; 10–30 µΩ·cm in narrow contacts due to grain boundary scattering).
- CVD-compatible: WF₆ precursor reduces cleanly to W metal at 300–450°C.
- Excellent step coverage in high-AR contacts when properly nucleated.
- Does not diffuse into silicon or dielectrics at process temperatures.
**Tungsten Contact Process Flow**
```
1. Contact etch: RIE through ILD to silicide (NiPtSi) — AR ~8:1 to 15:1
2. Pre-clean: Dilute HF to remove native oxide from silicide surface
3. Barrier/adhesion: TiN ALD (2–5 nm) — provides adhesion + diffusion barrier
(TiN also acts as nucleation layer)
4. W nucleation (optional): SiH₄ reduction of WF₆ → thin W nucleation layer (2–3 nm)
Si + 2WF₆ → 2W + SiF₄ ↑ (reaction avoids fluorine attack on silicide)
5. W bulk fill: H₂ reduction of WF₆ → fill contact
WF₆ + 3H₂ → W + 6HF (fast, bulk fill)
6. W CMP: Remove overburden → planar tungsten plug flush with ILD surface
```
**Nucleation Step Importance**
- WF₆ directly on TiN → TiN reacts with WF₆ (Ti + WF₆ → W + TiF₄) → TiN consumed → adhesion failure.
- SiH₄ nucleation: Si reduces WF₆ → forms thin W seed layer on TiN → bulk WF₆/H₂ can proceed on W seed.
- Alternative nucleation: B₂H₆ reduction → B₂H₆ + WF₆ → W nucleation (less common).
- Nucleation thickness: 3–5 nm needed for continuous coverage → each nm consumed reduces contact volume available for low-resistance W fill.
**Seam and Void Defects**
- W CVD deposits conformally → sidewall W grows toward center → can form seam or void at center of contact if growth rates imbalanced.
- **Keyhole void**: Entrance of contact closes before bottom fills → enclosed void → high resistance, potential open.
- Mitigation: Low-pressure W CVD (better step coverage), ALD-W nucleation + W bulk fill, or bottom-up fill.
**Bottom-Up Tungsten Fill**
- New approach at advanced nodes: Selectively grow W from bottom of contact → fills without seam.
- Uses thermal W ALD with inhibition chemistry → suppresses W growth on sidewalls → preferential bottom-up fill.
- Result: Seam-free W plug → lower resistance, better reliability.
**W Resistivity at Narrow Contacts**
- Bulk W resistivity: 5.6 µΩ·cm.
- At 10 nm contact diameter: Grain boundary and surface scattering → effective ρ = 30–80 µΩ·cm.
- TiN barrier (2 nm) in 10 nm contact: Consumes 40% of contact area → further increases Rc.
- Alternative metals at 3nm nodes: Mo (lower ρ at small scale), Ru (ALD capability, no nucleation issue).
**W CMP**
- W CMP removes overburden → leaves W flush with ILD.
- W CMP slurry: Fe(NO₃)₃ oxidizer + H₂O₂ + abrasive (alumina or silica) — acidic chemistry.
- Selectivity: W:TiN:SiO₂ ≈ 100:30:1 (optimize to clear W without dishing).
- W dishing: Center of wide W pads polishes faster → concave surface → contact height variation.
The tungsten plug is **the vertical connector of the CMOS world** — forming billions of ohmic contacts from source/drain silicide up to metal-1 on every chip, tungsten CVD fill with its nucleation-bulk two-step chemistry enables the high-aspect-ratio, void-free, low-resistance contacts that determine whether a transistor's on-current reaches its circuit load or is wasted as resistive voltage drop in the contact stack.