void

A void in semiconductor manufacturing refers to an empty cavity, bubble, or unfilled region trapped within a deposited thin film, typically occurring during the filling of high-aspect-ratio features such as trenches, vias, and contact holes. Voids represent one of the most serious defect types because they can cause electrical opens in metal interconnects, increase resistance in partially filled conductors, create reliability failures through electromigration or stress migration, compromise dielectric isolation between devices, and cause CMP dishing or erosion when exposed during planarization. Voids form through several mechanisms depending on the deposition process. In CVD, the most common cause is premature pinch-off: non-conformal deposition creates overhangs at the top corners of trenches that grow together and seal the opening before the trench bottom is completely filled, trapping a keyhole-shaped void. The void shape depends on the deposition conformality — highly non-conformal processes create large triangular voids, while moderately conformal processes create narrow keyhole or seam voids along the feature centerline. In copper electroplating, voids can form from insufficient wetting, inadequate suppressor/accelerator additive balance, or gas bubble entrapment during the plating process. In PVD, the inherent directionality of sputtered material makes void-free fill of features with aspect ratios above 1:1 nearly impossible without reflow techniques. Post-deposition voids can also form through stress-induced voiding (stress migration) where mechanical stresses in metal lines drive atom diffusion that creates voids at grain boundaries or interfaces, and through electromigration where current-induced atomic movement creates voids at cathode ends of metal lines. Detection methods include cross-sectional SEM/TEM for physical analysis, acoustic microscopy for buried voids, electrical testing for open or high-resistance failures, and X-ray tomography for non-destructive volumetric inspection. Prevention strategies focus on selecting deposition technologies with appropriate gap-fill capability (HDP-CVD, FCVD, ALD, or superconformal electroplating) matched to the feature geometry requirements of each technology node.