wafer bonding technique

**Wafer Bonding Technology** is the **advanced integration technique that permanently joins two processed wafers face-to-face — enabling 3D integration, backside processing, and heterogeneous material combination by physically bonding wafer surfaces at the atomic level through direct (fusion), adhesive, or hybrid (Cu-Cu + oxide-oxide) bonding methods, forming the foundation of 3D stacked architectures including HBM memory, 3D V-Cache, image sensors, and the emerging backside power delivery network**. **Bonding Types** **Direct (Fusion) Bonding** - Two ultra-clean, ultra-flat oxide or silicon surfaces are brought into contact at room temperature. Van der Waals forces create an initial bond that is strengthened by annealing (200-400°C). - Surface requirements: roughness <0.5 nm RMS, particle-free (a single 1 μm particle prevents bonding over mm² area), hydrophilic surface activation (plasma or chemical). - Used for: SOI wafer manufacturing, image sensor (BSI-CIS) fabrication, MEMS. **Hybrid Bonding (Cu-Cu + Oxide-Oxide)** - Both dielectric (SiO₂/SiCN) and metal (Cu pads) on each wafer surface bond simultaneously. - Process: (1) CMP both wafers to atomic flatness. (2) Plasma activate surfaces. (3) Align and bond at room temperature (oxide-oxide bond forms first). (4) Anneal at 200-300°C — Cu pads expand due to CTE and make contact, forming Cu-Cu metallic bonds. - Cu pad pitch: 1-10 μm (current production). Research: <1 μm (sub-micron hybrid bonding). - **Electrical Connection**: Each Cu-Cu bond provides a direct electrical path between the stacked wafers — no TSVs or bumps needed at the bonding interface. Bond density: millions of connections per cm². **Adhesive Bonding** - Polymer adhesive (BCB, SU-8, polyimide) between wafers. Lower surface quality requirements but no electrical connection at the bond interface (separate TSVs needed). - Used for: lower-cost 3D integration, MEMS packaging. **Wafer-to-Wafer vs. Die-to-Wafer** - **W2W**: Entire wafer bonded to entire wafer. Highest throughput and alignment accuracy (<200 nm overlay). But: both wafers must have identical die sizes and arrays — no mix-and-match of different die. - **D2W**: Individual dies (Known Good Die) picked from a source wafer and placed onto a target wafer, then batch-bonded. Allows mixing die of different sizes and testing before bonding (eliminates yield loss from bonding bad die). Alignment accuracy: 0.5-1.5 μm (current), <0.5 μm (advanced). **Applications** - **3D DRAM (HBM)**: 4-16 DRAM dies stacked and bonded with TSV connections. HBM3: 12-die stack, 1024 bit-wide bus, >800 GB/s per stack. - **AMD 3D V-Cache**: 64 MB SRAM cache die bonded on top of the CCD using hybrid bonding. Adds 3× L3 cache without increasing CCD area. - **Image Sensors (BSI-CIS)**: Pixel array wafer bonded face-to-face with logic wafer. Allows independent optimization of photodiode (image) and readout (logic) processes. Sony Stacked CMOS sensor = W2W hybrid bonded. - **Backside Power Delivery**: After front-side BEOL, the wafer is bonded face-down to a carrier, thinned from the back, and backside metal is processed. Carrier bonding/debonding is a critical process step. Wafer Bonding Technology is **the 3D stacking enabler that transcends the limitations of planar integration** — creating multi-layer chip architectures with millions of vertical electrical connections at sub-micron pitch, providing the bandwidth, density, and heterogeneous integration capabilities that AI and HPC workloads demand.