wafer map analysis

**Wafer map analysis** is the **systematic interpretation of die-level pass-fail and parametric bin distributions across a wafer to diagnose process health** - it combines visualization and statistics to identify spatial signatures that pure scalar yield numbers miss. **What Is Wafer Map Analysis?** - **Definition**: Examination of spatial bin patterns, gradients, and clusters on die maps. - **Data Sources**: Wafer sort binning, parametric test values, and inline metrology overlays. - **Pattern Types**: Rings, radial gradients, edge-loss, quadrants, stripes, and random scatter. - **Analysis Scale**: Single wafer, lot-level aggregation, and tool-by-tool trend comparison. **Why Wafer Map Analysis Matters** - **Root Cause Speed**: Spatial signatures often indicate specific process modules. - **Yield Improvement**: Pattern-aware correction can recover significant good die count. - **Risk Screening**: Outlier regions can trigger additional reliability checks. - **Tool Control**: Repeating map motifs reveal calibration drift or hardware degradation. - **Design Feedback**: Systematic map effects can indicate layout sensitivity hotspots. **How It Is Used in Practice** - **Visual Pass**: Rapid heatmap review by bin and key parametric tests. - **Statistical Pass**: Quantify gradients, correlation lengths, and defect density hotspots. - **Action Loop**: Link signatures to process modules, run split experiments, verify improvement. Wafer map analysis is **the operational language of yield engineering** - it converts millions of die-level measurements into targeted process decisions that improve both quality and cost.