wet cleaning surface preparation
**Wet Cleaning and Surface Preparation** — Essential process steps performed dozens of times during CMOS fabrication to remove contaminants, particles, native oxides, and etch residues that would otherwise degrade device performance, reliability, and yield.
**RCA Clean Chemistry** — The foundational RCA cleaning sequence developed at Radio Corporation of America remains the basis for modern wet cleaning processes. SC-1 (Standard Clean 1) using NH4OH/H2O2/H2O at 50–70°C removes organic contaminants and particles through oxidative dissolution and electrostatic repulsion from the negatively charged oxide surface. SC-2 (Standard Clean 2) using HCl/H2O2/H2O removes metallic contaminants through complexation and dissolution. Dilute HF (DHF) at 0.1–1% concentration strips chemical oxide between SC-1 and SC-2 steps, exposing fresh silicon surfaces and lifting embedded particles. Modern implementations use diluted chemistries (100:1 to 1000:1 dilution ratios) to reduce chemical consumption and surface roughening while maintaining cleaning efficiency.
**Megasonic and Physical Cleaning** — Megasonic energy at 0.8–3MHz frequencies generates controlled cavitation and acoustic streaming that dislodge particles from wafer surfaces without the damage associated with lower-frequency ultrasonic cleaning. As particle removal targets decrease below 20nm, the acoustic energy required approaches the damage threshold for fragile structures — patterned wafer cleaning requires careful power optimization to balance removal efficiency against feature damage. Spray-based cleaning using high-velocity aerosol droplets provides an alternative physical removal mechanism with reduced pattern damage risk for sensitive front-end-of-line structures.
**Pre-Gate and Pre-Epitaxy Surface Preparation** — Gate oxide and epitaxial growth quality depend critically on surface cleanliness and termination. Pre-gate cleaning must achieve metallic contamination levels below 10⁹ atoms/cm² and particle densities below 0.1 particles/cm² at sizes above 30nm. Hydrogen-terminated silicon surfaces produced by final DHF treatment provide the ideal starting surface for thermal oxidation and epitaxial growth. Surface micro-roughness must be maintained below 0.15nm RMS to prevent gate oxide integrity degradation and interface state generation.
**Post-Etch and Post-Ash Residue Removal** — Plasma etch and photoresist strip processes leave polymeric residues, metallic contaminants, and modified surface layers that require specialized cleaning. Semi-aqueous and organic solvent-based strippers dissolve fluorocarbon polymers and sidewall passivation residues. Copper-compatible cleaning chemistries avoid oxidizing or corroding exposed metal surfaces during back-end-of-line processing. Dilute hydrofluoric acid with surfactant additives removes post-ash oxide residues while controlling surface wetting and preventing watermark defects during drying.
**Wet cleaning and surface preparation processes are performed at over 100 steps in a modern CMOS flow, making cleaning technology a critical yield enabler whose effectiveness directly determines the electrical quality and reliability of every subsequently formed interface and film.**