wet etch
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**Semiconductor Etching** is the **controlled removal of material from wafer surfaces through chemical (wet) or plasma-based (dry) processes** — transferring the patterns defined by lithography into the underlying films by selectively removing exposed material while protecting covered areas, with etch precision at advanced nodes requiring atomic-level control of depth, profile, and selectivity.
**Wet Etch vs. Dry Etch**
| Property | Wet Etch | Dry Etch (Plasma) |
|----------|---------|------------------|
| Mechanism | Chemical dissolution | Ion bombardment + chemical |
| Profile | Isotropic (undercuts mask) | Anisotropic (vertical sidewalls) |
| Selectivity | Very high (>100:1) | Moderate (5-50:1) |
| Rate control | Temperature, concentration | Power, pressure, chemistry |
| Damage | Minimal | Ion damage possible |
| Cost | Low | High (vacuum equipment) |
| Use | Cleaning, stripping, bulk removal | Pattern transfer, precision etch |
**Dry Etch Mechanisms**
1. **Sputtering (Physical)**: High-energy ions physically knock atoms off surface — pure physical, non-selective.
2. **Chemical Etching**: Reactive gas species chemically react with surface — selective but isotropic.
3. **RIE (Reactive Ion Etch)**: Combination — ions provide directionality, chemistry provides selectivity.
4. **DRIE (Deep RIE / Bosch Process)**: Alternating etch and passivation cycles — high aspect ratio trenches.
**Common Etch Chemistries**
| Material | Etch Gas | Byproduct | Application |
|----------|---------|-----------|------------|
| Silicon | SF₆, Cl₂, HBr | SiF₄, SiCl₄ | Gate, fin etch |
| SiO₂ | CF₄, C₄F₈, CHF₃ | SiF₄, CO | Contact, via etch |
| Si₃N₄ | CHF₃, CH₂F₂ | SiF₄, HCN | Spacer etch |
| Metal (W/Al) | Cl₂, BCl₃ | WCl₆, AlCl₃ | Metal patterning |
| Organic (resist) | O₂ | CO₂, H₂O | Resist strip (ashing) |
**Critical Etch Parameters**
- **Etch Rate**: nm/min of material removed. Must be uniform across wafer.
- **Selectivity**: Ratio of etch rates (target material vs. mask/underlayer).
- Example: Oxide etch with 50:1 selectivity to Si → etches oxide 50x faster than Si.
- **Profile**: Vertical (90°), tapered (80-85°), or re-entrant (>90°).
- Advanced nodes need near-vertical profiles for pattern fidelity.
- **Uniformity**: < 3% variation across 300mm wafer.
- **Loading**: Etch rate depends on pattern density — open areas etch faster.
**Advanced Node Etch Challenges**
- **Atomic Layer Etch (ALE)**: Remove one atomic layer per cycle — ultimate precision.
- **HAR Etch**: 3D NAND requires etching 200+ layer stacks with aspect ratios > 50:1.
- **Self-Aligned Etch**: Etch processes that automatically align to existing features — no lithography needed.
- **Etch selectivity crisis**: Materials become similar at advanced nodes → harder to achieve high selectivity.
Semiconductor etching is **the subtractive counterpart to deposition** — together they sculpt the three-dimensional nanoscale structures that form transistors and interconnects, and the ability to etch with atomic-level precision is a fundamental requirement for every new technology node.