what is a through silicon via
A through-silicon via, or TSV, is a microscopic vertical electrical connection drilled directly through a piece of silicon, allowing signals to pass straight up and down between stacked chips rather than routing around the edges — a key enabling technology behind stacking multiple dies on top of each other inside advanced chip packages.
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{
"rows": [
{ "type": "nodes", "items": [
{ "title": "Want to stack multiple dies vertically", "sub": "e.g. memory stacked on top of a processor", "tone": "neutral" }
]},
{ "type": "arrow" },
{ "type": "group", "title": "TSVs connect the stacked layers", "items": [
{ "title": "Vertical conductive path drilled through silicon", "sub": "connects each layer directly to the one above/below", "tone": "green" }
]},
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{ "type": "nodes", "items": [
{ "title": "Short, high-bandwidth vertical connections", "sub": "far shorter than routing signals around the chip's edges", "tone": "orange" }
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```
**TSVs solve the problem of connecting stacked dies without relying on much longer, slower connections routed around the outside edges.** Without a vertical connection, signals traveling between two stacked dies would have to route out to the edge of one die, across a connection, and back in to the other — a TSV instead drills straight through the silicon itself, creating the shortest possible electrical path between two stacked layers, which meaningfully improves both signal speed and power efficiency compared to routing around the perimeter.
```svg
```
| Connection method | Signal path length | Typical use |
|---|---|---|
| Wire routed around die edge | Longer — around the perimeter | Older, non-stacked packaging |
| Through-silicon via (TSV) | Shortest — straight vertical path | Modern stacked-die and chiplet packages |
**Manufacturing TSVs reliably at scale is a genuinely difficult process, which is a major reason stacked-die packaging took years to mature into a mainstream technique.** Drilling extremely small, precise holes through silicon and filling them with conductive material without damaging the surrounding circuitry or introducing defects requires specialized equipment and tightly controlled processes — the manufacturing difficulty of TSVs was one of the key engineering hurdles that had to be solved before die-stacking became commercially practical at scale.
**TSVs are a core enabling technology behind high-bandwidth memory, one of the most important applications of stacked-die packaging today.** Stacking multiple memory dies on top of each other and connecting them with TSVs creates a memory module with dramatically more bandwidth than a single flat memory chip could offer in the same footprint — this stacked, TSV-connected approach to memory has become essential for feeding data fast enough to modern AI accelerators and other bandwidth-hungry chips.
**Using TSVs involves real tradeoffs in manufacturing cost and complexity, meaning they're used deliberately rather than universally.** Adding TSVs to a die requires extra manufacturing steps beyond standard chip fabrication, increasing cost and introducing new potential points of failure — chipmakers weigh that added cost and complexity against the real performance benefit of vertical stacking, choosing TSV-based designs specifically for applications, like high-bandwidth memory, where that tradeoff clearly pays off.
Read the through-silicon via through a shortcut lens: rather than routing a connection the long way around a chip's edge, a TSV drills straight through the silicon itself, creating the shortest, fastest possible path between stacked dies — a small but essential piece of engineering behind the broader trend toward stacking and combining multiple dies into one advanced package.