alignment mark
An alignment mark is a small reference fiducial pattern etched onto a wafer during an early process step, used by a lithography scanner to precisely position each subsequent patterned layer relative to the layers already built beneath it.
```flowchart
{
"rows": [
{ "type": "nodes", "items": [
{ "title": "Alignment marks patterned onto the wafer early on", "sub": "small fiducial reference features fixed at known locations", "tone": "neutral" }
]},
{ "type": "arrow" },
{ "type": "group", "title": "Scanner reads alignment marks before each new layer", "items": [
{ "title": "Wafer position and orientation measured against marks", "sub": "new layer's pattern positioned relative to existing layers", "tone": "blue" }
]},
{ "type": "arrow" },
{ "type": "nodes", "items": [
{ "title": "Each layer lands precisely aligned to the layers below", "sub": "critical for features that must connect across layers", "tone": "green" }
]}
]
}
```
**Alignment marks exist because a chip is built from dozens of separately patterned layers stacked on top of each other, and those layers must line up with extremely fine precision for features like vias and transistor gates to connect correctly.** Since a lithography scanner has no inherent way to know exactly where a wafer's existing patterns sit once the wafer is loaded, alignment marks provide small, precisely known fiducial reference points the scanner can optically detect, letting it calculate the wafer's exact position and orientation and position each new layer's pattern correctly relative to everything already built beneath it.
```svg
```
```svg
```
| Aspect | Without reliable alignment marks | With alignment marks |
|---|---|---|
| Layer-to-layer positioning | Uncertain, error-prone | Precisely measured and corrected |
| Overlay accuracy | Poor | Tight, within design tolerances |
| Feature connectivity across layers | At risk | Reliable |
| Common use | Not practical for multi-layer chips | Standard on every patterned wafer |
**Alignment marks are typically placed in multiple locations across a wafer, since measuring position at several points lets the scanner also detect and correct for slight wafer distortion, rotation, or scaling, not just simple positional offset.** Because a wafer isn't always perfectly rigid or perfectly positioned, and can shift or distort slightly during processing, using multiple alignment marks spread across different wafer locations gives the scanner enough information to correct for more complex misalignment patterns than a single reference point could reveal on its own.
**Alignment mark design must account for the fact that marks patterned early in the process may become partially obscured or altered by later process steps like deposition or polishing, requiring marks robust enough to remain reliably detectable.** Because a wafer goes through many additional processing steps after its alignment marks are first patterned, mark designs and the optical detection systems that read them are engineered to remain reliably measurable even after being partially covered or altered by subsequent film depositions or polishing steps.
**Alignment accuracy requirements have tightened considerably as feature sizes have shrunk, since the acceptable margin for layer-to-layer misalignment shrinks right along with the features themselves.** Because increasingly small transistor and interconnect features leave correspondingly less room for layer-to-layer positioning error, lithography scanners have had to continuously improve the precision with which they read alignment marks and position wafers, making alignment mark technology and scanner alignment systems a continuously advancing area of process technology.
Read the alignment mark through a tailoring-notch lens: much like small notches cut into fabric pieces let a tailor line up seams precisely when assembling a garment from separately cut pieces, alignment marks let a lithography scanner line up each new patterned layer precisely against everything already built on the wafer.