edge placement error
Edge placement error, or EPE, is the total deviation between where a feature's edge is actually formed on a chip and where it was intended to be, combining both lithography overlay misalignment and pattern size variation into a single measure that determines whether adjacent features stay safely separated.
```flowchart
{
"rows": [
{ "type": "nodes", "items": [
{ "title": "Multiple sources of positioning and sizing variation", "sub": "overlay misalignment, critical dimension variation, and more", "tone": "neutral" }
]},
{ "type": "arrow" },
{ "type": "group", "title": "EPE combines these into one total deviation measure", "items": [
{ "title": "Total distance a feature edge lands from its intended spot", "sub": "captures the combined effect, not just one source alone", "tone": "blue" }
]},
{ "type": "arrow" },
{ "type": "nodes", "items": [
{ "title": "Determines whether adjacent features stay safely separated", "sub": "excessive EPE risks shorts, opens, or other defects", "tone": "green" }
]}
]
}
```
**EPE exists because no single measurement, like overlay accuracy or critical dimension control alone, fully captures whether two adjacent features on a chip will actually end up safely separated from each other in the finished device.** Since a feature's final edge position depends on multiple compounding factors, including how precisely one patterned layer aligns with the layer beneath it and how consistently the feature's own size is controlled, edge placement error combines these contributing factors into a single total measure of how far a feature's actual edge lands from its intended position, providing a more complete picture of real-world spacing risk than any one factor considered alone.
```svg
```
```svg
```
| Aspect | Overlay accuracy alone | Edge placement error |
|---|---|---|
| What it measures | Layer-to-layer alignment only | Combined alignment and size deviation |
| Completeness of risk picture | Partial | More complete |
| Sensitivity to critical dimension variation | Not captured | Captured |
| Common use | One input among several | Composite metric used for design margin |
**EPE has become an increasingly critical metric as feature spacing has shrunk to the point where the margin for any combined positioning error has become extremely tight.** As chip features have continued shrinking, the physical space available between adjacent features has shrunk right along with them, meaning even relatively small combined overlay and dimension variations can now consume a meaningful fraction of the remaining spacing margin, making EPE a far more critical metric at advanced nodes than it was at older, more spacious process generations.
**Controlling EPE requires improvements across multiple separate process steps simultaneously, since it's a composite measure rather than something a single process improvement alone can fully address.** Because EPE combines contributions from multiple distinct sources, including lithography overlay accuracy and pattern size control, meaningfully reducing EPE typically requires coordinated improvements across several different process steps at once, rather than any single process fix being sufficient on its own.
**EPE is used as a key input to determining safe design spacing rules, since designers need to know how much margin to leave between features given the total positioning variation the process can realistically deliver.** Because chip designers need to leave enough physical spacing between features to reliably avoid shorts or other defects even under worst-case positioning variation, EPE, as a composite measure of that realistic variation, directly informs the spacing design rules used when laying out a chip for a given process technology.
Read edge placement error through a parking-space lens: rather than looking only at how well a car is centered in its spot, EPE also accounts for how much the car itself varies in size from one instance to the next, capturing the full combined risk of it actually encroaching into the next space over.