what is chip yield
Yield is the percentage of chips on a wafer that come out good enough to sell, and it is the single number that decides more about a chip's real-world cost than almost anything else in the entire manufacturing process — a design that is technically brilliant but yields poorly can be more expensive to produce than a simpler design that yields well, because every bad die on a wafer still consumed the exact same expensive lithography, etch, and deposition steps as a good one.
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{ "type": "nodes", "items": [
{ "title": "One wafer, hundreds of identical-by-design dies", "sub": "same mask set, same process run", "tone": "neutral" }
]},
{ "type": "arrow" },
{ "type": "group", "title": "Test every die", "note": "defects and process variation hit dies unevenly", "items": [
{ "title": "Defect-free, passes spec", "sub": "sellable good die", "tone": "green" },
{ "title": "Contains a killer defect", "sub": "fails, scrapped", "tone": "blue" }
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{ "type": "nodes", "items": [
{ "title": "Yield = good dies ÷ total dies", "sub": "the number that sets real per-chip cost", "tone": "orange" }
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```
**A "killer defect" is any flaw large enough, in the wrong place, to break a die's function — and it takes only one to fail an otherwise perfect chip.** A stray particle landing during a critical patterning step, a small lithography or etch variation, or a contamination event can each turn one specific die into scrap while its neighbors on the same wafer come out fine. Because a modern chip has millions or billions of transistors packed into a small area, even a tiny density of defects across the wafer can fail a meaningful share of the dies on it.
```svg
```
**Yield is why die size is a direct economic decision, not just a design or performance choice.** For a fixed defect density, a larger die has a statistically higher chance of overlapping at least one killer defect than a smaller die, simply because it covers more area where a defect could land — this is why chip designers treat die size as a lever against cost, and why splitting one large chip into several smaller connected chiplets, each yielding better on its own, has become a major strategy for keeping cost under control as designs get more complex.
**Yield improves over the life of a process node as the fab learns to eliminate defect sources, which is the real story behind a new node's early high prices.** A brand-new process typically launches with lower yield because engineers are still hunting down every contamination source, tool drift, and marginal design rule interaction; yield climbs steadily over the following months and years as those issues get fixed, which is a major reason products built on a freshly launched node often cost more per chip than the same design would cost a year or two later on a matured version of that same node.
| Term | What it means | Why it matters |
|---|---|---|
| Yield | Good dies ÷ total dies on a wafer, as a percentage | Directly sets the real per-chip manufacturing cost |
| Killer defect | A flaw severe enough to fail a die | One is enough to scrap an otherwise good chip |
| Defect density | Average defects per unit area on a wafer | Combined with die size, predicts expected yield |
| Yield ramp | Yield improving over a process node's lifetime | Explains why early-node chips cost more than mature-node chips |
**Yield also explains why some products only appear well after a fab first announces a new manufacturing process, rather than launching alongside it.** A company will often hold back its most defect-sensitive, highest-volume product until yield on a new node has climbed to an economically viable level, launching smaller or less area-hungry chips first — those simply have a lower chance of overlapping a killer defect, so they can go to market profitably long before yield is good enough to support a large, high-volume flagship design.
Read yield through a defect-density-times-area lens: the two numbers that actually decide how many good chips come off a wafer are how many defects the process introduces per square millimeter and how many square millimeters each individual die covers — everything else in chip economics, from die-size decisions to chiplet strategies to why a brand-new node starts out expensive, ultimately traces back to that one multiplication.