what is your lead time

**Lead times vary by service and complexity**, ranging from **6-8 weeks for prototyping to 12-24 months for complete ASIC development** — with fast-track options available for urgent projects and transparent milestone tracking throughout the process. **Fabrication Lead Times** **Prototyping (MPW - Multi-Project Wafer)**: - **Mature Nodes (180nm-65nm)**: 6-8 weeks from tape-out to wafer delivery - **Advanced Nodes (40nm-28nm)**: 8-10 weeks from tape-out to wafer delivery - **Leading-Edge (14nm-7nm)**: 10-14 weeks from tape-out to wafer delivery - **Schedule**: Fixed monthly or quarterly MPW runs - **Minimum**: 5 wafers, shared with other customers **Dedicated Production Runs**: - **Mature Nodes (180nm-65nm)**: 8-12 weeks from order to wafer delivery - **Advanced Nodes (40nm-28nm)**: 10-14 weeks from order to wafer delivery - **Leading-Edge (14nm-7nm)**: 12-16 weeks from order to wafer delivery - **Minimum**: 25 wafers for dedicated run - **Priority**: Available for additional cost (reduce by 20-30%) **Hot Lot / Expedited Service**: - **Premium Service**: 30-50% faster than standard lead time - **Mature Nodes**: 4-6 weeks (vs 8-12 weeks standard) - **Advanced Nodes**: 6-8 weeks (vs 10-14 weeks standard) - **Cost Premium**: 50-100% additional wafer cost - **Availability**: Subject to fab capacity **Packaging Lead Times** **Wire Bond Packaging**: - **Standard**: 3-4 weeks from wafer delivery to packaged units - **Expedited**: 2 weeks with premium (30% additional cost) - **Volume**: 1K-100K units per run - **Setup**: 1-2 weeks for new package type (tooling, qualification) **Flip Chip Packaging**: - **Standard**: 4-6 weeks from wafer delivery to packaged units - **Expedited**: 3 weeks with premium (40% additional cost) - **Volume**: 500-50K units per run - **Setup**: 2-4 weeks for new package (bumping, substrate, qualification) **Advanced Packaging (2.5D/3D)**: - **Standard**: 6-10 weeks from wafer delivery to packaged units - **Complex**: 8-12 weeks for multi-die stacking - **Volume**: 100-10K units per run - **Setup**: 4-8 weeks (interposer design, TSV, hybrid bonding setup) **Testing Lead Times** **Wafer Sort**: - **Standard**: 1-2 weeks after wafer delivery - **Expedited**: 3-5 days with premium - **Setup**: 2-4 weeks for test program development (first time) - **Throughput**: 50-200 wafers per week depending on test complexity **Final Test**: - **Standard**: 1-2 weeks after packaging - **Expedited**: 3-5 days with premium - **Burn-In**: Add 1-2 weeks for HTOL (48-168 hours at temperature) - **Setup**: 3-6 weeks for test program development (first time) **Reliability Qualification**: - **JEDEC Standard**: 12-16 weeks (all tests: TC, HTOL, HAST, MSL, etc.) - **Automotive (AEC-Q100)**: 16-20 weeks (extended testing requirements) - **Medical (ISO 13485)**: 16-24 weeks (includes biocompatibility if needed) - **Accelerated**: 8-12 weeks with higher stress conditions (customer risk) **Complete ASIC Development Timelines** **Simple Digital ASIC (10K-100K gates, 180nm)**: - **Specification**: 1 month - **RTL Design**: 2-3 months - **Verification**: 2-3 months - **Physical Design**: 2-3 months - **Tape-Out**: 2 weeks - **Fabrication**: 2-3 months - **Packaging & Test**: 1-2 months - **Total**: 12-15 months from start to production-ready chips **Medium Digital ASIC (100K-1M gates, 65nm)**: - **Specification**: 1-2 months - **RTL Design**: 3-6 months - **Verification**: 3-6 months - **Physical Design**: 3-6 months - **Tape-Out**: 3-4 weeks - **Fabrication**: 3-4 months - **Packaging & Test**: 2-3 months - **Total**: 18-24 months **Complex SoC (1M-10M gates, 28nm)**: - **Specification**: 2-3 months - **RTL Design**: 6-12 months - **Verification**: 6-12 months - **Physical Design**: 6-12 months - **Tape-Out**: 4-6 weeks - **Fabrication**: 3-4 months - **Packaging & Test**: 2-3 months - **Qualification**: 3-6 months - **Total**: 24-36 months **Analog & Mixed-Signal Timelines**: - **Simple Analog Block**: 6-9 months (design + fab + test) - **Medium Complexity**: 12-18 months (ADC, PLL, power management) - **Complex Mixed-Signal**: 18-30 months (RF transceiver, high-speed SerDes) - **Note**: Analog requires more iteration and characterization time **Timeline Acceleration Options** **Fast-Track Design**: - **Larger Team**: Add engineers to parallelize work (20-30% faster) - **Extended Hours**: Overtime and weekend work (10-20% faster) - **Cost Premium**: 30-50% additional design cost - **Best For**: Time-to-market critical projects **Hot Lot Fabrication**: - **Priority Processing**: Move ahead in fab queue - **Reduced Cycle Time**: 30-50% faster than standard - **Cost Premium**: 50-100% additional wafer cost - **Availability**: Limited slots, book in advance **Expedited Packaging/Test**: - **Priority Scheduling**: Jump queue for assembly and test - **Dedicated Resources**: Dedicated equipment and operators - **Cost Premium**: 30-50% additional cost - **Turnaround**: 50% faster than standard **Parallel Processing**: - **Overlap Phases**: Start packaging before all wafers complete - **Risk**: May need to scrap work if issues found - **Time Savings**: 2-4 weeks - **Cost**: Minimal additional cost, customer assumes risk **Factors Affecting Lead Time** **Design Complexity**: - **Gate Count**: More gates = longer design and verification time - **IP Integration**: Licensed IP faster than custom development - **Analog Content**: Analog blocks require more iteration - **Verification**: Complex verification extends timeline **Process Node**: - **Mature Nodes**: Faster, more predictable (proven processes) - **Advanced Nodes**: Longer due to complexity (multi-patterning, EUV) - **Custom Processes**: Add 3-6 months for process development **Fab Capacity**: - **High Demand**: May extend lead times by 2-4 weeks - **Low Demand**: May accelerate by 1-2 weeks - **Allocation**: Long-term customers get priority - **Seasonality**: Q4 typically busiest (consumer products) **First-Time vs Repeat**: - **First Tape-Out**: Includes setup, qualification, learning curve - **Respin/Shrink**: 30-50% faster (reuse test programs, packaging) - **Production Repeat**: Fastest (established flow, no setup) **Quality Requirements**: - **Commercial**: Standard qualification (12-16 weeks) - **Automotive**: Extended qualification (16-20 weeks) - **Medical**: Most extensive (16-24 weeks) - **Military**: Longest (20-30 weeks with radiation testing) **Typical Project Milestones & Timeline** **Month 0**: Contract signed, project kickoff **Month 1-2**: Specification finalized, architecture defined **Month 3-8**: RTL design and verification (parallel) **Month 9-14**: Physical design and timing closure **Month 15**: Tape-out, mask data preparation **Month 16-18**: Wafer fabrication (12 weeks) **Month 19**: Wafer sort and die selection **Month 20**: Packaging and assembly **Month 21**: Final test and characterization **Month 22-24**: Qualification and production ramp **How to Minimize Your Timeline** **Early Planning**: - Start with clear, detailed specifications - Make technology decisions early (process, IP, packaging) - Secure funding and approvals upfront - Book fab capacity in advance **Efficient Execution**: - Use proven IP blocks vs custom development - Parallel design and verification activities - Regular design reviews to catch issues early - Fast decision-making on tradeoffs **Risk Management**: - Conservative design margins (easier timing closure) - Thorough verification (avoid respin) - DFM review before tape-out (improve yield) - Prototype testing before volume production **Lead Time Tracking** **Project Portal**: - Real-time status updates - Milestone completion tracking - Gantt chart visualization - Alert notifications for delays **Weekly Reports**: - Progress summary - Completed activities - Upcoming milestones - Issues and risks **Monthly Reviews**: - Detailed progress review - Schedule assessment - Budget tracking - Risk mitigation planning **Contact for Timeline Discussion**: - **Email**: [email protected] - **Phone**: +1 (408) 555-0100 - **Request**: Detailed project timeline based on your requirements Chip Foundry Services provides **realistic, achievable timelines** with transparent tracking and proactive communication to keep your project on schedule from concept to production.