<svg xmlns="http://www.w3.org/2000/svg" viewBox="0 0 760 470" font-family="Segoe UI,Helvetica,Arial,sans-serif"><rect x="0" y="0" width="760" height="470" rx="14" fill="#0d1117"/><text x="20" y="30" fill="#e6edf3" font-size="19" font-weight="700">3D IC: go vertical — bond two wafers, or build the second tier in place</text><text x="20" y="50" fill="#8b949e" font-size="12.5">Parallel 3D bonds finished wafers via TSV or Cu-Cu; monolithic 3D grows a new transistor tier on top, in place</text><!-- ===== PANEL 1 ===== --><rect x="20" y="66" width="226" height="298" rx="7" fill="#0c141d" stroke="#30363d"/><text x="36" y="92" fill="#38bdf8" font-size="14" font-weight="700">1 · Two ways to go vertical</text><!-- LEFT: parallel bond --><text x="83" y="110" text-anchor="middle" fill="#9fd8ef" font-size="10.5" font-weight="700">Parallel — bond</text><rect x="44" y="124" width="78" height="20" rx="2" fill="#233041" stroke="#6f8fb0"/><text x="83" y="138" text-anchor="middle" fill="#adb5bd" font-size="9">die 2</text><line x1="44" y1="145" x2="122" y2="145" stroke="#38bdf8" stroke-width="1" stroke-dasharray="3 2"/><rect x="44" y="146" width="78" height="20" rx="2" fill="#1c2733" stroke="#6f8fb0"/><text x="83" y="160" text-anchor="middle" fill="#adb5bd" font-size="9">die 1</text><rect x="48" y="168" width="70" height="9" fill="#3a2c1e" stroke="#5a4632"/><g stroke="#b8732e" stroke-width="1.6"><line x1="60" y1="124" x2="60" y2="177"/><line x1="90" y1="124" x2="90" y2="177"/><line x1="108" y1="124" x2="108" y2="177"/></g><text x="83" y="190" text-anchor="middle" fill="#c98a2e" font-size="8">TSV / Cu-Cu bond</text><!-- RIGHT: monolithic --><text x="186" y="110" text-anchor="middle" fill="#7ee6c0" font-size="10.5" font-weight="700">Monolithic — in place</text><rect x="150" y="124" width="72" height="16" rx="2" fill="#16332a" stroke="#3f9d6f"/><text x="186" y="136" text-anchor="middle" fill="#adb5bd" font-size="8.5">tier 2</text><rect x="150" y="150" width="72" height="16" rx="2" fill="#1c2733" stroke="#3f9d6f"/><text x="186" y="162" text-anchor="middle" fill="#adb5bd" font-size="8.5">tier 1</text><rect x="154" y="168" width="64" height="9" fill="#3a2c1e" stroke="#5a4632"/><g stroke="#7ee6c0" stroke-width="0.9"><line x1="158" y1="140" x2="158" y2="150"/><line x1="166" y1="140" x2="166" y2="150"/><line x1="174" y1="140" x2="174" y2="150"/><line x1="182" y1="140" x2="182" y2="150"/><line x1="190" y1="140" x2="190" y2="150"/><line x1="198" y1="140" x2="198" y2="150"/><line x1="206" y1="140" x2="206" y2="150"/><line x1="214" y1="140" x2="214" y2="150"/></g><text x="186" y="190" text-anchor="middle" fill="#7ee6c0" font-size="8">inter-tier via (nm)</text><text x="36" y="214" fill="#adb5bd" font-size="11">Parallel bonds two finished</text><text x="36" y="229" fill="#adb5bd" font-size="11">wafers; monolithic grows tier 2</text><text x="36" y="254" fill="#7ee6c0" font-size="11" font-weight="700">directly on tier 1 — no bond.</text><text x="36" y="279" fill="#8b949e" font-size="10.5">Inter-tier vias are far denser</text><text x="36" y="293" fill="#8b949e" font-size="10.5">than any bonded connection —</text><text x="36" y="307" fill="#8b949e" font-size="10.5">that is the whole point.</text><!-- ===== PANEL 2 ===== --><rect x="267" y="66" width="226" height="298" rx="7" fill="#0c141d" stroke="#30363d"/><text x="283" y="92" fill="#38bdf8" font-size="14" font-weight="700">2 · Vertical pitch ladder</text><text x="283" y="120" fill="#c9d1d9" font-size="10.5">microbump</text><text x="474" y="120" text-anchor="end" fill="#e0913a" font-size="9.5">~30–40 µm</text><g fill="#b8732e"><circle cx="288" cy="130" r="1.9"/><circle cx="310" cy="130" r="1.9"/><circle cx="332" cy="130" r="1.9"/><circle cx="354" cy="130" r="1.9"/><circle cx="376" cy="130" r="1.9"/><circle cx="398" cy="130" r="1.9"/></g><text x="283" y="160" fill="#c9d1d9" font-size="10.5">TSV</text><text x="474" y="160" text-anchor="end" fill="#e0b13a" font-size="9.5">~5–10 µm</text><g fill="#b8732e"><circle cx="288" cy="170" r="1.9"/><circle cx="301" cy="170" r="1.9"/><circle cx="314" cy="170" r="1.9"/><circle cx="327" cy="170" r="1.9"/><circle cx="340" cy="170" r="1.9"/><circle cx="353" cy="170" r="1.9"/><circle cx="366" cy="170" r="1.9"/><circle cx="379" cy="170" r="1.9"/><circle cx="392" cy="170" r="1.9"/></g><text x="283" y="200" fill="#c9d1d9" font-size="10.5">Cu-Cu hybrid bond</text><text x="474" y="200" text-anchor="end" fill="#7ee6c0" font-size="9.5">&lt; 1 µm</text><g fill="#7ee6c0"><circle cx="288" cy="210" r="1.7"/><circle cx="295" cy="210" r="1.7"/><circle cx="302" cy="210" r="1.7"/><circle cx="309" cy="210" r="1.7"/><circle cx="316" cy="210" r="1.7"/><circle cx="323" cy="210" r="1.7"/><circle cx="330" cy="210" r="1.7"/><circle cx="337" cy="210" r="1.7"/><circle cx="344" cy="210" r="1.7"/><circle cx="351" cy="210" r="1.7"/><circle cx="358" cy="210" r="1.7"/><circle cx="365" cy="210" r="1.7"/><circle cx="372" cy="210" r="1.7"/><circle cx="379" cy="210" r="1.7"/><circle cx="386" cy="210" r="1.7"/><circle cx="393" cy="210" r="1.7"/></g><text x="283" y="240" fill="#c9d1d9" font-size="10.5">monolithic inter-tier via</text><text x="474" y="240" text-anchor="end" fill="#a99cf0" font-size="9.5">~50–100 nm</text><g fill="#a99cf0"><circle cx="287" cy="250" r="1.4"/><circle cx="291" cy="250" r="1.4"/><circle cx="295" cy="250" r="1.4"/><circle cx="299" cy="250" r="1.4"/><circle cx="303" cy="250" r="1.4"/><circle cx="307" cy="250" r="1.4"/><circle cx="311" cy="250" r="1.4"/><circle cx="315" cy="250" r="1.4"/><circle cx="319" cy="250" r="1.4"/><circle cx="323" cy="250" r="1.4"/><circle cx="327" cy="250" r="1.4"/><circle cx="331" cy="250" r="1.4"/><circle cx="335" cy="250" r="1.4"/><circle cx="339" cy="250" r="1.4"/><circle cx="343" cy="250" r="1.4"/><circle cx="347" cy="250" r="1.4"/><circle cx="351" cy="250" r="1.4"/><circle cx="355" cy="250" r="1.4"/><circle cx="359" cy="250" r="1.4"/><circle cx="363" cy="250" r="1.4"/></g><line x1="283" y1="266" x2="477" y2="266" stroke="#30363d"/><text x="283" y="286" fill="#adb5bd" font-size="10.5">Finer vertical pitch = finer 3D</text><text x="283" y="301" fill="#adb5bd" font-size="10.5">partitioning: whole chips, then</text><text x="283" y="316" fill="#adb5bd" font-size="10.5">blocks, then individual gates.</text><text x="283" y="341" fill="#8b949e" font-size="10">Bonding buys density; monolithic</text><text x="283" y="354" fill="#8b949e" font-size="10">buys another 100x on top.</text><!-- ===== PANEL 3 ===== --><rect x="514" y="66" width="226" height="298" rx="7" fill="#0c141d" stroke="#30363d"/><text x="530" y="92" fill="#38bdf8" font-size="14" font-weight="700">3 · Thermal budget &amp; payoffs</text><text x="530" y="112" fill="#34d399" font-size="11.5" font-weight="700">Payoffs</text><g fill="#34d399"><circle cx="534" cy="125" r="2.6"/><circle cx="534" cy="140" r="2.6"/><circle cx="534" cy="155" r="2.6"/><circle cx="534" cy="170" r="2.6"/></g><text x="544" y="128" fill="#c9d1d9" font-size="10.5">Shorter global wires</text><text x="544" y="143" fill="#c9d1d9" font-size="10.5">Memory directly over logic</text><text x="544" y="158" fill="#c9d1d9" font-size="10.5">CFET: nFET over pFET, tiny cells</text><text x="544" y="173" fill="#c9d1d9" font-size="10.5">New floorplans across tiers</text><line x1="530" y1="185" x2="724" y2="185" stroke="#30363d"/><text x="530" y="205" fill="#e0b13a" font-size="11.5" font-weight="700">The thermal wall</text><g fill="#e0b13a"><circle cx="534" cy="218" r="2.6"/><circle cx="534" cy="233" r="2.6"/><circle cx="534" cy="248" r="2.6"/><circle cx="534" cy="263" r="2.6"/></g><text x="544" y="221" fill="#adb5bd" font-size="10.5">Tier-2 built cold (&lt;~500 °C) so</text><text x="544" y="234" fill="#adb5bd" font-size="10.5">tier-1 devices survive</text><text x="544" y="251" fill="#adb5bd" font-size="10.5">Buried tiers are hard to cool</text><text x="544" y="266" fill="#adb5bd" font-size="10.5">Yield multiplies across tiers</text><text x="530" y="292" fill="#f87171" font-size="10.5" font-weight="700">Heat removal and low-temp device</text><text x="530" y="306" fill="#f87171" font-size="10.5" font-weight="700">quality are the real limits.</text><!-- ===== BOTTOM CARDS ===== --><rect x="20" y="384" width="226" height="70" rx="7" fill="#111a24" stroke="#30363d"/><text x="36" y="406" fill="#38bdf8" font-size="12.5" font-weight="700">Bond or build-in-place</text><text x="36" y="424" fill="#adb5bd" font-size="10">Stack and bond two finished wafers,</text><text x="36" y="437" fill="#adb5bd" font-size="10">or grow a second transistor tier</text><text x="36" y="450" fill="#adb5bd" font-size="10">sequentially on the first.</text><rect x="267" y="384" width="226" height="70" rx="7" fill="#111a24" stroke="#30363d"/><text x="283" y="406" fill="#a99cf0" font-size="12.5" font-weight="700">Density sets the payoff</text><text x="283" y="424" fill="#adb5bd" font-size="10">From TSV µm to monolithic-via nm,</text><text x="283" y="437" fill="#adb5bd" font-size="10">finer vertical pitch moves you from</text><text x="283" y="450" fill="#adb5bd" font-size="10">chip-level to gate-level 3D.</text><rect x="514" y="384" width="226" height="70" rx="7" fill="#111a24" stroke="#30363d"/><text x="530" y="406" fill="#e0b13a" font-size="12.5" font-weight="700">Heat &amp; thermal budget bite</text><text x="530" y="424" fill="#adb5bd" font-size="10">Buried tiers are hard to cool, and</text><text x="530" y="437" fill="#adb5bd" font-size="10">monolithic's top tier must be built</text><text x="530" y="450" fill="#adb5bd" font-size="10">cold enough to spare the bottom.</text></svg>

3D Integration Methods are the architectural approaches that stack multiple device layers or dies vertically with high-density interconnections — achieving 10-100× higher interconnect density than 2D packaging, reducing wire length by 50-70%, and enabling heterogeneous integration of logic, memory, and analog functions with bandwidth exceeding 1 TB/s per mm² of interface area.

Monolithic 3D Integration:

• Sequential Layer Transfer: fabricate first transistor layer on bulk wafer; deposit and planarize interlayer dielectric (ILD); transfer or grow second transistor layer directly on top using low-temperature (<400°C) processes compatible with underlying CMOS; repeat for additional layers
• Low-Temperature Transistors: IGZO (indium gallium zinc oxide) TFTs processed at 300-350°C provide mobility 10-40 cm²/V·s; polysilicon TFTs with laser annealing achieve mobility 50-200 cm²/V·s; these enable logic and memory in upper tiers without damaging lower-tier devices
• Inter-Tier Vias (ITV): vertical connections between transistor layers with pitch 50-200nm (10-100× denser than TSV); fabricated using standard via processes; resistance 0.5-5 Ω per via depending on aspect ratio and metal fill quality
• Advantages: ultimate interconnect density enabling fine-grained partitioning (gate-level or block-level); no alignment tolerance issues since layers are lithographically defined; demonstrated by CEA-Leti CoolCube™ technology with two transistor tiers and <100nm ITV pitch

Die-to-Wafer (D2W) Bonding:

• Known Good Die (KGD): pre-tested dies from one wafer are picked and placed onto a second wafer with alignment accuracy ±0.5-2μm; hybrid bonding or micro-bump interconnection; enables mixing dies from different wafers, technologies, or vendors
• Throughput Challenge: sequential die placement limits throughput to 50-200 dies per hour depending on die size and alignment accuracy requirements; Besi DB900 die bonder achieves ±0.3μm placement accuracy with vision-based alignment
• Yield Multiplication: only known-good dies are integrated; if base wafer yield is 80% and stacked die yield is 90%, D2W achieves 72% system yield vs 64% for W2W (wafer-to-wafer) where bad dies on either wafer create bad stacks
• HBM Integration: High Bandwidth Memory uses D2W to stack 8-12 DRAM dies on a logic base; each die tested before stacking ensures high system yield; TSV pitch 40-55μm with Cu micro-bumps providing >1000 connections per die

Wafer-to-Wafer (W2W) Bonding:

• Parallel Processing: entire wafers bonded simultaneously with alignment accuracy ±0.5-1.5μm across 300mm diameter; highest throughput (20-40 wafer pairs per hour) but requires matched wafer sizes and high individual wafer yields
• Hybrid Bonding: simultaneous Cu-Cu metallic bonding and oxide-oxide dielectric bonding at 200-300°C; no solder or underfill required; achieves <10μm pitch interconnects with <5 mΩ resistance per connection; TSMC SoIC (System on Integrated Chips) and Intel Foveros use hybrid bonding
• Alignment Marks: IR-transparent alignment through bonded wafers enables multi-tier stacking; alignment accuracy degrades with each tier (tier 1: ±0.5μm, tier 2: ±1μm, tier 3: ±1.5μm) due to accumulated thermal and mechanical distortion
• Thermal Budget: bonding temperature <300°C preserves BEOL (back-end-of-line) integrity; lower temperatures reduce thermal stress (CTE mismatch between Si: 2.6 ppm/K and Cu: 16.5 ppm/K causes warpage) but require longer bonding time or higher pressure

Heterogeneous Integration:

• Chiplet Ecosystems: integrate dies from different process nodes and technologies; 5nm logic + 28nm analog + 14nm SRAM + III-V RF on a common interposer or through 3D stacking; UCIe (Universal Chiplet Interconnect Express) standard enables multi-vendor chiplet integration
• Memory-on-Logic: stack HBM or hybrid memory cube (HMC) directly on processor die; bandwidth 1-2 TB/s vs 50-100 GB/s for DDR5; power efficiency 5-10 pJ/bit vs 20-50 pJ/bit for off-package memory; AMD MI300 and NVIDIA H100 use HBM3 stacks
• Imager Stacking: backside-illuminated (BSI) image sensor die bonded to ISP (image signal processor) logic die; pixel pitch 0.8-1.4μm with Cu-Cu hybrid bonding; eliminates wire bond parasitics improving readout speed to >10 Gpixels/s
• Thermal Management: 3D stacks generate 50-200 W/cm² heat flux; through-silicon cooling with microchannels (50-100μm width) or thermal TSVs (Cu-filled vias for heat extraction) required; junction temperatures must stay <85°C for reliability

3D integration methods are the pathway to continued performance scaling beyond Moore's Law — enabling heterogeneous systems that combine the best technology for each function while achieving interconnect densities and bandwidths impossible in 2D, fundamentally transforming semiconductor architecture from planar to volumetric.