Monolithic 3D Integration is sequential stacking of CMOS transistor layers on the same silicon wafer using low-temperature top-tier processing to avoid damaging lower tiers—enabling ultra-high-density 3D circuits with microscopic inter-layer vias.

Bottom-Up Sequential Process:

• Tier 1 (bottom): fabricated at standard temperature (800°C+), conventional CMOS flow
• Tier 2 (top): deposited on top of tier 1, constrained to <400°C maximum temperature
• Top-tier limitations: polysilicon quality reduced, doping profiles less aggressive
• Tier integration: transistor optimization sacrificed for low-temperature compatibility

Inter-Tier Via (ITV) Technology:

• ITV density: >10⁸ per mm² theoretical (vs ~10⁷/mm² TSV conventional bonding)
• Via formation: laser drilling or photolithography through dielectric layer
• Via metallization: plated copper similar to standard via process
• Electrical connectivity: enables direct vertical signal routing between tiers

Sequential 3D Process Flow:

• Define tier 1 standard CMOS (poly, metal 1-5)
• Stop before metal 6: insert inter-layer dielectric (amorphous silicon or oxide)
• Deposit mono-crystalline or poly-crystalline silicon for tier 2 base
• Implant dopants, activate at reduced temperature
• Grow oxide, deposit poly, pattern gates for tier 2 transistors
• Complete tier 2 metallization normally

Thermal Constraint Challenge:

• Dopant diffusion: intrinsic dopant motion in tier 2 minimized by low T, reducing yield
• Metallurgical quality: reduced short-channel effects control
• Defect generation: thermal budget consumed in tier 1, tier 2 less optimized
• Workaround: post-layer crystallization via rapid thermal processing (RTP)

Applications and Benefits:

• Logic + SRAM stacking: compute layer + memory layer
• Density advantage: 3-5x improvement vs 2D equivalent footprint
• Latency improvement: minimal interconnect between logic/memory
• Cost: offset by process complexity, lower yield than 2D

Commercial Development:

• Leti CoolCube: research prototype, demonstrated functionality
• Imec alternative approaches: substrate transfer monolithic 3D
• Industry adoption: challenged by lack of EDA tool support, limited design methodologies
• Future: more viable as chiplet integration matures (chiplet alternative)

Monolithic 3D remains promising but not yet mainstream—competing with chiplet 2.5D/3D approaches which leverage proven CMOS and bonding processes at higher maturity level.