3D NAND flash is the memory architecture that escapes planar scaling limits by stacking hundreds of storage layers vertically — each layer is a word-line (gate) wrapping a vertical channel string, so density scales by adding layers rather than shrinking lithography. Samsung's V-NAND (2013) proved the concept at 24 layers; by 2025 the industry ships 200+ layer products (Samsung 236L, Micron 232L, SK Hynix 238L), and 300–400 layer designs are in development. 3D NAND stores the bits that train and serve every large language model — a single hyperscaler AI cluster requires petabytes of flash storage.

Why planar NAND hit a wall. Planar (2D) NAND shrank the floating-gate cell to ~15 nm half-pitch, but at that scale: (1) fewer than 10 electrons represent a programmed state, making data retention statistical; (2) cell-to-cell capacitive coupling causes read disturb and program disturb; (3) the tunnel oxide can no longer be thinned without leakage — endurance collapses below 1000 P/E cycles. Going vertical solved all three: the cell in 3D NAND is physically large (~30–50 nm gate length), so oxide quality and charge margins are comfortable — the hard problem moved from lithography to etching deep, straight holes.

The charge-trap cell. 3D NAND abandoned the conductive floating gate in favor of a charge-trap flash (CTF) cell, where electrons are stored in a silicon-nitride (Si₃N₄) dielectric layer sandwiched between tunnel oxide and blocking oxide — the ONO (oxide–nitride–oxide) stack. Charge is localized in the nitride traps rather than free to redistribute, which eliminates inter-cell coupling through the floating gate. The threshold-voltage shift from stored charge:

$$\Delta V_t = \frac{Q_{\text{stored}}}{C_{\text{ONO}}} = \frac{q \cdot N_t \cdot t_{\text{N}}}{(\varepsilon_{\text{ox}}/t_{\text{block}}) + (\varepsilon_{\text{N}}/t_{\text{N}}) + (\varepsilon_{\text{ox}}/t_{\text{tunnel}})}$$

where $N_t$ is the trapped-electron density, $t_{\text{N}}$ is nitride thickness, and the denominator is the effective ONO capacitance per unit area.

Architecture — the vertical channel string. A 3D NAND array is built by:

1. Depositing a tall alternating stack of sacrificial layers (SiN or poly-Si) and oxide (SiO₂) — one pair per word-line layer. 2. Etching high-aspect-ratio channel holes (HAR etch: diameter ~100–130 nm, depth 5–10 µm, aspect ratio 50:1 to 80:1 in current products). 3. Depositing the ONO charge-trap films and a polysilicon channel conformally inside each hole. 4. Replacing the sacrificial layers with tungsten word-lines through slit trenches (the "gate-last" or "replacement-gate" flow).

Each vertical string connects a bit-line contact at the top to a common source plate at the bottom, with select gates (SSL/GSL) that isolate individual strings during read/program.

Multi-deck stacking. Beyond ~100 layers, etching a single continuous channel hole becomes impractical (the aspect ratio exceeds equipment limits). The solution: fabricate two (or three) shorter stacks ("decks") independently, then bond them together — either by a polysilicon interface or wafer-bonding the upper deck directly. Each deck is ~100–130 layers with its own channel-hole etch. Alignment between decks at the channel junction is critical; misalignment creates a resistance bump that degrades read speed and noise margin.

CMOS-under-array (CuA) / CMOS-bonded-array (CBA). In early 3D NAND, peripheral CMOS circuits (page buffers, decoders, charge pumps) sat beside the array, consuming ~30% of die area. CuA places the CMOS under the memory stack, recovering that area for storage. CBA (SK Hynix, Micron) goes further: fabricate the CMOS on a separate wafer, bond it face-to-face with the memory array wafer, then etch the channel holes through the memory stack landing on the CMOS wafer's metal pads. This decouples CMOS logic scaling from memory-stack processing, allowing each to use its optimal technology.

The killer process step — high-aspect-ratio (HAR) etch. Etching a 5–10 µm deep hole through 200+ alternating oxide/nitride layers at >60:1 aspect ratio is the single hardest etch in semiconductor manufacturing. Requirements: near-vertical profile (taper <0.1°), no bowing, no twisting, and landing within a 10 nm target at the bottom. The etch uses carbon-fluorine chemistry (C₄F₈/C₄F₆ + O₂ + Ar) in a high-density plasma at cryogenic wafer temperatures (−20 to −60°C) to form a protective polymer sidewall that prevents lateral etching. Each new layer generation demands either better etch (deeper single-deck) or multi-deck bonding.

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Bits per cell — SLC to QLC. Each charge-trap cell can store multiple bits by programming the threshold voltage to one of $2^n$ distinct levels:

Moving from TLC to QLC quadruples bit density per cell at the cost of tighter Vt margins, longer program times (ISPP with finer voltage steps), and more sophisticated ECC (LDPC codes with 200+ parity bits per 2 KB page).

Reliability fundamentals. 3D NAND reliability is governed by: (1) charge loss — electrons de-trap from the nitride layer over time, shifting Vt down (data retention, specified at 85°C for 1 year); (2) program disturb — high WL voltages during programming neighbor cells push parasitic charge into adjacent cells; (3) read disturb — repeated read-pass voltages on unselected WL slowly inject charge into cells above/below the target; (4) cell-to-cell variability — polysilicon grain boundaries in the vertical channel create random trap sites that shift Vt distributions. Error correction (BCH → LDPC → LDPC with soft-decision reads) compensates, but at the cost of read latency.

What 3D NAND means for AI infrastructure. A single GPT-4-class training run reads and writes hundreds of terabytes of checkpoint data. The training cluster's storage subsystem — invariably flash-based (NVMe SSDs) — must sustain multi-TB/s aggregate bandwidth with endurance to survive thousands of training iterations. The move to QLC and PLC, combined with 200+ layer stacking, keeps $/GB falling at ~20%/year — enabling the petabyte-scale datasets that feed modern AI without breaking the datacenter cost model.