3D Sequential Monolithic Integration is the advanced transistor stacking technology where multiple active device tiers are fabricated one on top of another on a single wafer using sequential processing — achieving the highest possible inter-tier connection density (billions of vias per mm²) compared to any bonded 3D approach, at the cost of the severe thermal constraint that upper tier processing must occur at temperatures low enough (< 500°C) to avoid damaging the metal interconnects and transistors of lower tiers already fabricated.

Why Sequential (Monolithic) 3D

• 3D bonded (W2W/D2W): Two separately processed wafers bonded → lowest thermal budget issue → but limited inter-tier density (microbump: µm pitch).
• Sequential monolithic: One processing run, multiple tiers grown/deposited in sequence → billions of inter-tier connections per mm² → true fine-grained 3D integration.
• Applications: Tier 1 = NMOS logic; Tier 2 = PMOS logic → CFET (Complementary FET); or Tier 1 = logic; Tier 2 = SRAM → cache-on-logic.

Thermal Budget Constraint

• Lower tier: Standard CMOS high-temp processing (S/D anneal 1000–1100°C, silicide, contacts).
• After lower tier: Copper BEOL deposited → max temperature now limited to 400–450°C.
• Upper tier transistors: Must be formed at < 500°C → cannot use standard high-temperature processing.
• Low-temperature transistor options:
• Laser anneal: Nanosecond laser heats only surface layer → upper tier annealed at 1000°C → lower tier sees < 5°C rise → spatially selective.
• Low-temperature epi: RPCVD SiGe channel at 450°C → adequate activation without bulk anneal.
• Amorphous oxide semiconductor (IGZO): Excellent TFT (thin-film transistor) at < 300°C → for memory select transistors.

CFET (Complementary FET)

• Ultimate expression of monolithic 3D: NMOS nanosheet on bottom, PMOS nanosheet on top → one transistor height serves both N and P devices.
• Standard CMOS cell: PMOS and NMOS side-by-side → cell height ~6T (6 tracks).
• CFET: PMOS stacked on NMOS → cell height ~3T → 2× area reduction for same function.
• Challenges: PMOS must be formed at < 500°C due to lower NMOS copper interconnects.
• Status: Intel (RibbonFET → path to CFET), Imec, TSMC → research; projected production 2030+.

Imec Sequential 3D Process

1. Lower tier: Standard CMOS (nMOS at 3nm node with W contacts). 2. CMP planarize → dielectric fill. 3. Bond alignment mark layer → deposit new Si seed layer or epitaxial Si at low temperature. 4. Upper tier Si: PECVD amorphous Si at 300°C → laser crystallize → seed EPI. 5. Upper tier transistors: Laser anneal only → S/D at < 500°C constraint → solid phase epitaxial regrowth (SPER). 6. Inter-tier vias: Very dense (< 40nm pitch) → connect upper to lower tier.

IGZO (Indium-Gallium-Zinc Oxide) Stacking

• Amorphous oxide semiconductor: IGZO TFT processed at 200–300°C → pure low-temperature backend.
• Memory select transistor on top of NAND flash or DRAM → 3D NAND gate transistor or DRAM access transistor.
• Samsung/Micron/SK Hynix: IGZO select transistors for 3D NAND → extends scalability of vertical NAND.
• Advantage: Very low leakage (> 10⁻²² A at room T) → excellent data retention for DRAM (4× longer refresh interval).

Inter-Tier Connection Density

3D sequential monolithic integration is the frontier of semiconductor scaling that treats vertical dimension as a new scaling axis — by stacking functional transistor tiers with via density a billion times higher than bondable chiplets can achieve, sequential 3D integration creates the possibility of true compute-on-memory, where processing logic sits within 10nm of SRAM arrays without any off-chip bottleneck, a vision that drives intensive research into low-temperature transistor processing and laser anneal technology that may eventually deliver the next leap in semiconductor density equivalent to several traditional node generations of lateral shrinkage.