3D Stacked Chip Design: Vertical Integration via TSV and Bonding — high-density memory-on-logic stacking enabling extreme bandwidth and power delivery with thermal management challenges

3D Stacking Technologies

• Through-Silicon Via (TSV): vertical copper interconnect through wafer, enables die-to-die connections with ~1-10 µm pitch
• Face-to-Face Bonding: direct metal-to-metal bonding at sub-µm pitch (100-300 nm), enables fine-grain chiplet interconnect vs coarser interposer-based stacking
• Hybrid Bonding: copper + dielectric bonding combines metal and insulator bonding for reliability, enables ~µm vertical interconnect pitch

Memory-on-Logic Configurations

• HBM Integration: high-bandwidth memory stacked directly on processor logic (NVIDIA H100 + HBM3e, AMD EPYC + 3D V-Cache)
• HBM + Logic via Interposer: older approach (HBM on interposer, logic below), larger pitch, higher latency
• SRAM-on-Logic (Backside SRAM): Intel Lakefield (3D backside SRAM for L3 cache), enables massive cache without sacrificing compute area
• AMD 3D V-Cache: dedicated SRAM stacked on CPU die, 3-tier die stack (compute + cache + interposer)

Power Delivery in 3D Stacks

• Backside Power Delivery Network (PDN): power rail on rear face of die (back-side of silicon), supplies power to active front-side circuit
• Via Density: backside TSV/micro-vias carry VDD/GND from back to front, massive via count (10s of thousands) enables ultra-low impedance
• Power Density: stacked memory + logic increases heat generation per area, backside PDN mitigates by delivering power more efficiently (shorter path, lower L/R)

Thermal Management Challenges

• Heat Flow: stacked dies trap heat (poor lateral heat spreading), vertical heat conduction path becomes thermal bottleneck
• Hot Spot Mitigation: micro-channel cooling (water jets between dies), thermal interface material (TIM) between die layers (graphite, copper foam)
• Temperature Gradients: 20-40°C difference between top/bottom of stack, impacts reliability (electromigration, NBTI) and performance (frequency derating)
• Thermal Design Power (TDP): constraints on power dissipation, 300+ W for CPU+GPU systems requires active liquid cooling

Design Constraints in 3D

• Keep-Out Zone (KOZ): area around TSV restricted (no logic/memory to avoid stress concentration), reduces effective die area by 10-15%
• Stress and Warpage: thermal mismatch between Si (11 ppm/K) and Cu (16 ppm/K) creates residual stress, warpage affects bonding alignment and interconnect reliability
• Electromigration in TSV: vertical current density higher than lateral, reliability margin reduced, requires current limiting

Manufacturing Challenges

• Alignment and Bonding: face-to-face bonding needs µm-level alignment (expensive tools), bonding yield critical for economical 3D
• TSV Defects: void formation in TSV (copper oxidation, reflow), copper pumping (extrusion through oxide), detected via electrical test post-bonding
• Backside Thinning: wafer thinned to 50-100 µm for backside access (for backside PDN), reduces mechanical strength, risk of wafer breakage

Performance and Power Benefits

• Bandwidth: HBM+logic stacking achieves 5-10× memory bandwidth vs externally connected HBM (shorter traces, lower latency)
• Power Reduction: reduced voltage drop (lower I²R via shorter path), fewer voltage domains needed
• Latency: memory access latency reduced by 10-30 ns (internal stacking vs external), critical for real-time inference

Future Direction: 3D stacking extends Moore's Law via vertical scaling, roadmap includes chiplet stacking (multiple heterogeneous chiplets in one package), advanced packaging technologies (chiplet-to-chiplet micro-bumps).