Adaptive Voltage Scaling (AVS) is the closed-loop control technique that dynamically adjusts supply voltage based on real-time measurement of silicon speed margins — compensating for process variation, temperature drift, and aging effects to operate at the minimum voltage required for target frequency, reducing power consumption by 15-30% compared to fixed-voltage designs.

AVS System Architecture:

• Speed Monitor (Critical Path Replica): ring oscillator or delay chain replicating the timing-critical path of the design — its oscillation frequency directly reflects the silicon's actual speed at current voltage, temperature, and aging conditions
• AVS Controller: digital controller compares monitor frequency against target — if silicon is faster than required, voltage is reduced; if slower, voltage is increased to maintain timing margin
• Voltage Regulator Interface: controller sends voltage request to external VRM or on-chip regulator through SVI2/SVID/PMBus protocol — voltage step size of 5-10 mV provides fine-grained control
• Feedback Loop: closed-loop bandwidth of 1-100 kHz tracks thermal variations (seconds timescale) — too-fast response risks instability, too-slow response wastes power during thermal excursions

Speed Monitor Design:

• Ring Oscillator Monitor (ROSC): chain of inverters whose frequency correlates with standard cell delay — simple but doesn't perfectly track all critical path types (may miss setup/hold paths in different logic)
• Critical Path Monitor (CPM): replica of actual timing-critical path synthesized from standard cells — provides direct correlation to design margins but requires updating when timing path changes
• In-Situ Monitor: timing detector embedded in actual data paths that detects when signals arrive dangerously close to clock edge — provides true margin measurement but generates timing errors that must be corrected
• Multiple Monitors: 4-16 monitors distributed across the die capture local process and thermal variations — AVS controller uses worst-case (slowest) monitor to set voltage

Droop Compensation:

• Voltage Droop Events: sudden current transients (workload change) cause supply voltage to temporarily drop due to package/board inductance — droops of 50-100 mV lasting 10-100 ns can cause timing failures
• Droop Detector: fast comparator detects when supply drops below threshold — triggers immediate frequency reduction or pipeline stall within 1-2 clock cycles
• Proactive Droop Mitigation: digital current sensor detects workload transitions and pre-emptively adjusts clock frequency or reduces instruction issue rate before droop occurs — Intel 's Speed Shift technology implements this approach
• Droop Guardband: AVS target voltage includes margin for worst-case droop — reducing droop amplitude through improved PDN design enables lower AVS voltage setpoint

AVS is a critical power optimization technique in modern processors — by eliminating the fixed voltage guardbands required for worst-case process corners, AVS enables each individual die to operate at its optimum voltage, recovering the 20-30% power penalty that conservative fixed-voltage designs impose.