Advanced DRAM Fabrication is the memory manufacturing process that creates ultra-dense arrays of one-transistor, one-capacitor (1T1C) cells — where the relentless scaling of DRAM to sub-15 nm half-pitch requires buried wordline transistors, high-aspect-ratio capacitors (60:1+) with high-k dielectrics, and EUV lithography to deliver the 16-24 Gb/die densities at the low costs that modern computing demands for main memory.

DRAM Cell Architecture

Each DRAM cell stores one bit as charge on a capacitor, accessed through one transistor:

• Access Transistor: Buried channel device with recessed gate (buried wordline, bWL) in the silicon substrate. The bWL reduces the transistor footprint and improves electrostatic control.
• Storage Capacitor: Metal-insulator-metal (MIM) capacitor storing ~20-30 fF of charge. Must maintain sufficient charge for reliable sensing despite leakage.
• Cell Size: 6F² layout (F = minimum feature size). At F=13 nm: cell area = ~1014 nm² ≈ 0.001 μm².

Capacitor Scaling: The Core Challenge

As cell area shrinks, the capacitor must maintain ~20 fF in less footprint. Solutions:

• High Aspect Ratio: Pillar or cup-shaped capacitors extend vertically. Current AR: 60:1 to 80:1 (a ~500 nm tall cylinder with ~6-8 nm diameter). Mechanical collapse during wet processing is a critical challenge.
• High-k Dielectric Stack: ZrO₂/Al₂O₃/ZrO₂ (ZAZ) or HfO₂-based dielectric stacks with k=25-50 replace SiO₂ (k=3.9). Leakage current must be <1 fA/cell at 1V for 64 ms retention time.
• Electrode Material: TiN electrodes on both sides of the dielectric. Atomic layer deposition (ALD) coats the high-AR cylindrical capacitor conformally at angstrom precision.

Buried Wordline (bWL) Transistor

The access transistor gate is recessed into the silicon substrate: 1. Etch a trench into Si. 2. Grow gate dielectric (SiO₂ + high-k) on trench surfaces. 3. Fill with metal gate (TiN + W). 4. The channel wraps around the gate at the bottom of the trench, providing better gate control and lower leakage than planar transistors. 5. Saddle-fin geometry further improves subthreshold characteristics.

Fabrication Process Flow

1. STI Formation: Shallow trench isolation defines active areas. 2. Buried Wordline: Trench etch, gate dielectric, metal gate fill, recess, cap. 3. Bitline Contact: Self-aligned contact to the cell's drain. 4. Bitline Stack: Metal bitline (W or Cu) with precisely controlled spacing. 5. Storage Node Contact: Contact from cell to capacitor. 6. Capacitor Array: Mold layer deposition, high-AR etch, bottom electrode (TiN ALD), dielectric (ZrO₂/Al₂O₃ ALD), top electrode (TiN ALD). 7. Top Plate: Common top plate connects all capacitor top electrodes.

EUV Adoption in DRAM

Samsung (1b/1c nm class) and SK hynix introduced EUV for critical DRAM layers starting at the 12-14 nm half-pitch node:

• Active Area Patterning: Replaces SAQP for active island definition.
• Bitline/Wordline: Single EUV exposure replaces multi-patterning.
• Cost Benefit: Fewer masks and process steps despite expensive EUV scanner time.

DRAM vs. Logic Scaling

DRAM scaling is fundamentally limited by the capacitor: charge must be sufficient for reliable sensing, and leakage must be low enough for 64 ms retention. This creates a "capacitor wall" that forces increasingly exotic materials and 3D structures.

Advanced DRAM Fabrication is the manufacturing discipline that balances the contradictory demands of shrinking the world's most cost-sensitive semiconductor product — maintaining the charge storage, access speed, and retention time that DRAM requires while scaling cell area to keep pace with the exponentially growing memory demands of AI, mobile, and cloud computing.