Advanced Interface Bus (AIB) is an open-source die-to-die interconnect standard originally developed by Intel and released under the DARPA CHIPS program — providing a parallel, wide-bus physical layer interface for chiplet-to-chiplet communication that prioritized simplicity and energy efficiency over raw bandwidth, serving as the pioneering open D2D standard that paved the way for UCIe and demonstrated the viability of multi-vendor chiplet ecosystems.

What Is AIB?

• Definition: A die-to-die PHY (physical layer) specification that defines a parallel, source-synchronous interface for communication between chiplets within a package — using many slow lanes (2 Gbps each) rather than few fast lanes to minimize power consumption and design complexity.
• DARPA CHIPS Origin: AIB was developed as part of DARPA's Common Heterogeneous Integration and IP Reuse Strategies (CHIPS) program, which aimed to demonstrate that military and commercial systems could be built from interoperable chiplets rather than custom monolithic ASICs.
• Open-Source: Intel released the AIB specification and reference PHY design as open-source, enabling any company to implement AIB-compatible chiplets without licensing fees — a groundbreaking move that catalyzed the chiplet ecosystem.
• Parallel Architecture: AIB uses a wide parallel bus (up to 80 data lanes per column) running at 2 Gbps per lane — the short distances within a package (< 10 mm) make parallel signaling more energy-efficient than high-speed SerDes.

Why AIB Matters

• Chiplet Pioneer: AIB was the first open die-to-die standard, proving that chiplets from different vendors could interoperate — Intel's Stratix 10 FPGA used AIB to connect FPGA fabric to external chiplets, demonstrating the concept in production silicon.
• UCIe Foundation: AIB's success and lessons learned directly informed the development of UCIe — many AIB concepts (parallel signaling, microbump-based physical layer, protocol-agnostic PHY) were adopted and enhanced in UCIe.
• Low Power: AIB achieves ~0.5 pJ/bit energy efficiency — competitive with proprietary D2D interfaces and sufficient for most chiplet communication needs.
• DARPA Ecosystem: The CHIPS program produced multiple AIB-compatible chiplets from different organizations (Intel, Lockheed Martin, universities), demonstrating multi-vendor chiplet assembly for the first time.

AIB Specification

• Data Rate: 2 Gbps per lane (DDR signaling at 1 GHz clock).
• Lane Count: Up to 80 data lanes per column, with multiple columns per die edge.
• Bump Pitch: 55 μm micro-bump pitch on advanced packaging.
• Bandwidth: ~160 Gbps per column (80 lanes × 2 Gbps).
• Latency: < 5 ns (PHY-to-PHY).
• Power: ~0.5 pJ/bit.

AIB is the pioneering open-source die-to-die standard that launched the chiplet revolution — demonstrating through the DARPA CHIPS program that interoperable chiplets from multiple vendors could be assembled into functional systems, establishing the technical and ecosystem foundations that UCIe and the broader chiplet industry now build upon.