A through-silicon via (TSV) is a vertical metal connection that passes through a silicon die or interposer, carrying signals or power between its front and back surfaces.

TSVs make vertical integration practical. In HBM they connect stacked DRAM dies; in a 2.5D silicon interposer they carry connections down to the package substrate; in 3D ICs they link active layers directly.

Fabrication is a deep-via process. The flow etches a high-aspect-ratio hole, deposits an insulating liner plus barrier and seed layers, fills it with copper, then thins the wafer to reveal the opposite end.

Mechanical effects matter as much as resistance. Copper and silicon expand differently with temperature, creating stress and keep-out zones around the via. Void-free fill, wafer thinning, alignment, and bonding all affect yield and reliability.