Air gap technology replaces solid dielectric between metal lines with air (κ = 1.0), achieving the lowest possible capacitance for interconnect layers at the tightest pitches. Concept: after forming metal lines, selectively remove dielectric between lines, leaving air-filled voids that minimize coupling capacitance. Fabrication approaches: (1) Non-conformal deposition—deposit dielectric that pinches off at top before filling gap, trapping air void; (2) Selective removal—etch sacrificial dielectric between lines through access holes, seal with cap layer; (3) Self-aligned—use different dielectrics for via level vs. line level, selectively remove line-level dielectric. Typical air gap process: (1) Form Cu dual-damascene lines normally; (2) Selectively etch ILD between lines (using mask or self-aligned to via locations); (3) Deposit non-conformal cap to seal top while preserving air gap; (4) Continue with next metal level. Capacitance reduction: 20-30% compared to low-κ SiOCH for same pitch. Where used: tightest pitch local interconnect layers (M1-M4) where capacitance most impacts performance. Challenges: (1) Mechanical support—air gaps weaken structure, must maintain pillars at via locations; (2) CMP compatibility—gaps can collapse under CMP pressure; (3) Reliability—moisture ingress, metal corrosion if not properly sealed; (4) Process complexity—additional etch and deposition steps; (5) Yield—defects from incomplete sealing or gap collapse. Industry adoption: Intel (10nm+), TSMC (7nm for select layers)—selective use on critical layers, not all metal levels. Integration: air gaps typically combined with low-κ SiOCH on wider-pitch layers where mechanical strength matters more. Represents the ultimate capacitance reduction for BEOL but requires careful engineering trade-offs between electrical benefit and mechanical reliability.