Analog Layout Design is the specialized physical design discipline for analog and mixed-signal circuits where transistor matching, parasitic minimization, noise isolation, and thermal symmetry are achieved through manual, topology-aware layout techniques — because the random placement and routing algorithms used for digital design would produce analog circuits with unacceptable offset, noise, and distortion.

Why Analog Layout Requires Human Expertise

Digital circuits are binary — a transistor is either on or off, and timing margins accommodate variation. Analog circuits operate in the continuous domain — a 1 mV mismatch in a differential pair causes a measurable output offset; a parasitic capacitance of 10 fF shifts a pole frequency and degrades phase margin. The spatial arrangement of transistors on silicon determines these parasitics and mismatches at as much as a 10x influence on circuit performance.

Key Analog Layout Techniques

• Common-Centroid Layout: Matched transistor pairs (differential pairs, current mirrors) are arranged so that their geometric centroids coincide. This cancels first-order systematic gradients (oxide thickness, doping, temperature) across the layout. For a differential pair M1/M2, interdigitated layout (M1-M2-M2-M1) achieves common-centroid symmetry.
• Dummy Structures: Transistors at the array edges experience different etch and lithography environments than interior transistors. Dummy (non-functional) transistors are placed at the edges to equalize the manufacturing environment, ensuring that all active transistors see identical neighbors.
• Guard Rings: Substrate and N-well guard rings surround sensitive analog circuits (bias generators, bandgaps, ADCs) to collect substrate noise injected by digital switching. P+ guard rings tied to VSS collect holes; N+ guard rings tied to VDD collect electrons. Critical for mixed-signal design where digital noise couples through the shared substrate.
• Symmetrical Routing: Signal paths to matched devices must be routed with identical metal length, width, and via count. Asymmetric routing introduces systematic resistance and capacitance mismatch that the transistor-level matching cannot compensate.
• Shielding: Sensitive high-impedance nodes (op-amp inputs, reference voltages) are shielded by metal ground planes above and below to block capacitive coupling from digital aggressor nets.

Thermal Considerations

Power transistors (output stages, voltage regulators) generate heat that creates thermal gradients across the die. Temperature gradients shift Vth (~-2 mV/°C for NMOS) and create systematic mismatch in nearby precision circuits. Analog layout places thermal-sensitive circuits (bandgap references, bias generators) away from heat sources and uses interleaved/common-centroid topologies to cancel linear gradients.

Parasitic-Aware Design

Analog designers extract parasitics (R, C, L) after layout and re-simulate to verify that the circuit meets specifications with real layout parasitics. This post-layout simulation loop (layout → extract → simulate → modify layout) may iterate 5-20 times for critical blocks, making analog layout the most time-intensive step in mixed-signal chip design.

Analog Layout Design is the craft discipline where silicon geometry directly determines circuit precision — a domain where the designer's understanding of physics, process variation, and electromagnetic coupling is expressed through the spatial arrangement of every transistor, wire, and contact.