Analog/Mixed-Signal (AMS) Verification is the chip design verification discipline that validates the correct behavior of circuits containing both analog (continuous-time, continuous-value) and digital (discrete-time, discrete-value) components — requiring co-simulation of SPICE-level analog models with RTL digital models at system level, where the simulation complexity, convergence challenges, and the fundamentally different abstractions of analog and digital design make AMS verification one of the most time-consuming and error-prone aspects of SoC development.

The AMS Verification Challenge

A modern SoC contains: digital logic (billions of gates, verified at RTL with fast event-driven simulation), analog blocks (PLLs, ADCs, DACs, RF, power management — verified with SPICE at transistor level), and mixed-signal interfaces between them. The challenge: digital RTL simulation runs at millions of cycles per second; SPICE simulation runs at microseconds per second. Simulating the full chip at SPICE level is impossible — a 1 ms simulation of a billion-transistor chip would take years.

Co-Simulation Approaches

• SPICE + Verilog Co-Simulation: SPICE simulator handles analog blocks at transistor level; Verilog simulator handles digital blocks at RTL. A co-simulation interface (e.g., Cadence AMS Designer, Synopsys Custom Compiler with VCS) exchanges signals at analog-digital boundaries. Accurate but slow — only practical for small analog blocks with limited digital context.

• Real Number Modeling (RNM): Analog blocks modeled as behavioral functions in SystemVerilog using real-valued signals and continuous assignments. A PLL model evaluates frequency vs. control voltage using math functions, not transistors. 100-1000× faster than SPICE. Accuracy: 90-95% for functional verification. The standard approach for SoC-level AMS verification.

• Verilog-AMS: Formal mixed-signal HDL supporting continuous-time differential equations alongside discrete events. Models can express transfer functions, noise, and nonlinearity. Runs in dedicated AMS simulators (Cadence Spectre AMS). More accurate than RNM, slower than pure RTL.

• IBIS-AMI: Specifically for SerDes channel simulation. Behavioral models of TX/RX equalization exchanged between vendors without revealing transistor-level IP. Enables system-level link simulation at statistical (non-time-domain) speed.

Key Verification Scenarios

• Functional Correctness: Does the ADC output match the analog input within specification? Does the PLL lock to the target frequency? Does the voltage regulator maintain output within tolerance under load transients?
• Analog-Digital Interface Timing: Setup/hold violations at the analog-to-digital boundary where continuous signals are sampled by clock edges. Clock domain crossing between analog-generated clocks and digital clocks.
• Power Supply Effects: Digital switching noise coupling to analog supply rails through shared power distribution. Decoupling strategy verification requires power-aware simulation.
• Process Corners and Monte Carlo: Analog circuits are sensitive to process variation. Verification must cover FF/SS/TT corners and Monte Carlo mismatch for yield-critical specifications (ADC linearity, PLL jitter, regulator accuracy).

AMS Verification Flow

1. Block-Level SPICE: Transistor-level verification of each analog block against its specification. 2. RNM Model Development: Create behavioral models calibrated against SPICE results. 3. Top-Level AMS Simulation: Digital RTL + RNM analog models in a unified testbench. Run use cases, boot sequences, and system scenarios. 4. Mixed-Signal Regression: Automated regression suite with assertion-based checking on analog parameters (frequency, voltage, current thresholds).

AMS Verification is the integration bottleneck where analog and digital worlds collide — the verification discipline whose methodology and toolchain maturity determine whether a mixed-signal SoC works on first silicon or requires costly respins to fix analog-digital interaction bugs.