Analog-to-Digital Converter (ADC) Design is the mixed-signal circuit discipline that converts continuous analog signals (voltage, current) into discrete digital representations — where the choice of ADC architecture (SAR, Pipeline, Sigma-Delta, Flash) determines the achievable resolution (8-24 bits), sampling rate (kHz to GHz), power consumption (μW to watts), and area, making ADC design one of the most diverse and demanding specializations in chip design.

ADC Architectures

Flash ADC:

• 2^N−1 parallel comparators, each set to a different threshold voltage (resistor ladder). All comparators fire simultaneously — conversion in one clock cycle.
• Speed: fastest (up to 10+ GS/s). Resolution: limited to 6-8 bits (256 comparators for 8 bits). Power: high (exponential with resolution).
• Use: SerDes front-ends, oscilloscopes, radar.

SAR (Successive Approximation Register):

• Binary search algorithm: set MSB, compare, keep or clear, set next bit, repeat for N bits. Requires N comparison cycles per conversion.
• Speed: 1-500 MS/s. Resolution: 8-18 bits. Power: very low (1-100 μW for 12-bit at 1 MS/s). Area: smallest.
• Use: sensor interfaces, IoT, biomedical, low-power SoCs. The most widely used ADC architecture.

Pipeline ADC:

• Cascade of stages, each resolving 1-4 bits. Each stage computes a residue (analog remainder) that is amplified and passed to the next stage. Stages operate concurrently on successive samples (pipeline parallelism).
• Speed: 50 MS/s-1 GS/s. Resolution: 10-16 bits. Power: moderate (10-500 mW).
• Use: communications receivers, medical imaging, base stations.

Sigma-Delta (ΔΣ) ADC:

• Oversamples at many times Nyquist rate, uses a 1-bit quantizer in a feedback loop with noise-shaping. Digital decimation filter produces high-resolution output at lower rate.
• Speed: 10 Hz-10 MHz output rate. Resolution: 16-24 bits. Power: low-moderate.
• Use: audio (studio-quality recording), precision measurement, industrial sensors, weigh scales.

Key Performance Metrics

• ENOB (Effective Number of Bits): Actual resolution accounting for noise and distortion. ENOB = (SINAD − 1.76) / 6.02. A "12-bit" ADC with ENOB of 10.5 performs like a perfect 10.5-bit converter.
• SNDR/SINAD: Signal-to-noise-and-distortion ratio. Limits dynamic range.
• SFDR: Spurious-free dynamic range — ratio of fundamental to largest spur. Critical for RF applications where spurs cause false signals.
• DNL/INL: Differential/Integral nonlinearity — deviation from ideal transfer function. DNL < 1 LSB guarantees no missing codes.

Walden FoM (Figure of Merit)

FoM = Power / (2^ENOB × fs) measured in fJ/conversion-step. State-of-the-art: 1-5 fJ/conv-step for SAR ADCs in advanced CMOS. This metric enables fair comparison across architectures and process nodes.

Design Challenges at Advanced Nodes

• Reduced Supply Voltage: 0.7-0.8V supply at 5 nm limits comparator headroom and reference voltage range. Dynamic comparators and bootstrapped switches mitigate.
• Device Mismatch: Threshold voltage variation (σVt ∝ 1/√(W×L)) sets resolution limits for flash and SAR. Calibration (digital background, foreground) corrects systematic errors post-fabrication.
• Sampling Bandwidth: The sampling switch (transmission gate) must settle to N-bit accuracy within half a clock period. At 1 GS/s, 14 bits: settling to 0.006% in 500 ps requires >10 GHz bandwidth.

ADC Design is the interface between the analog physical world and the digital processing domain — the mixed-signal circuit whose resolution, speed, and power define the limits of what sensors can measure, what signals communications systems can receive, and what data AI systems can acquire.