Analog-to-Digital Converter (ADC) Design is the mixed-signal circuit discipline that converts continuous analog signals into discrete digital representations — where the architecture choice (SAR, pipeline, sigma-delta, flash) determines the achievable resolution (8-24 bits), sampling rate (1 kSPS to 100 GSPS), and power efficiency (fJ-pJ/conversion-step), making ADC design one of the most architecturally diverse and performance-critical challenges in chip design because the ADC is the gateway between the analog physical world and the digital processing domain.

Key Performance Metrics

• ENOB (Effective Number of Bits): Actual resolution accounting for noise and distortion. ENOB = (SINAD - 1.76) / 6.02.
• SNR (Signal-to-Noise Ratio): Ratio of signal power to noise power. Thermally limited by kT/C noise in the sampling capacitor.
• SFDR (Spurious-Free Dynamic Range): Distance from signal to the largest distortion harmonic.
• FoM (Figure of Merit): Energy per conversion step = Power / (2^ENOB × fs). State-of-art: <1 fJ/conversion-step for SAR ADCs.

ADC Architectures

• SAR (Successive Approximation Register): Binary search using a capacitive DAC. Each bit requires one comparison cycle — N bits in N clock cycles. Resolution: 8-18 bits. Speed: 1-500 MSPS. Extremely energy efficient (<10 fJ/step). Dominant for IoT, sensors, and moderate-speed applications.

• Pipeline ADC: Cascaded stages, each resolving 1.5-3 bits per stage with a residue amplifier passing the remainder to the next stage. Achieves high throughput (100 MSPS-1 GSPS) at medium resolution (10-14 bits). Requires accurate inter-stage gain — calibration-intensive.

• Sigma-Delta (ΔΣ) ADC: Oversamples the input at 64-512x the Nyquist rate, shapes quantization noise out of the signal band using feedback, then decimation-filters to the target resolution. Achieves the highest resolution (16-24 bits) at lower speeds (1 kSPS-10 MSPS). Ideal for audio, instrumentation, and sensor interfaces.

• Flash ADC: 2^N-1 parallel comparators simultaneously compare the input to all reference levels. Single-cycle conversion at the fastest possible speed (10-100 GSPS) but resolution limited to 4-8 bits by the exponential comparator count and power. Used in optical communication receivers and ultra-high-speed sampling.

• Time-Interleaved (TI) ADC: N parallel sub-ADCs (typically SAR) sample in rotation, multiplying effective sampling rate by N. Dominant architecture for 10+ GSPS converters in 5G, radar, and oscilloscopes. Mismatch between sub-ADCs (offset, gain, timing) creates spurs that require digital background calibration.

CMOS Scaling Impact on ADC Design

Smaller process nodes reduce switch capacitance and comparator delay (faster, lower power ADCs) but also reduce supply voltage (smaller signal swing, less headroom for analog circuits) and increase device mismatch (variability). Advanced ADC design increasingly relies on digital calibration to compensate for analog imperfections — trading transistors (cheap at small nodes) for improved analog accuracy.

ADC Design is the critical bridge between physics and computation — converting the continuous signals of the real world into the digital numbers that processors manipulate, where the converter's speed, resolution, and efficiency directly determine the capability of every sensing, communication, and measurement system.