Angled (Tilt) Ion Implantation

Keywords: angled implant,tilt implant,tilt angle implant,halo tilt,extension tilt implant,pocket implant tilt

Angled (Tilt) Ion Implantation is the ion implant technique where the wafer is tilted relative to the ion beam by 7–45°, allowing dopants to be introduced beneath overhanging structures (such as gate electrodes) to form halo pocket implants, adjust lateral channel profiles, or control LDD extension geometries — a critical process for controlling short-channel effects, threshold voltage roll-off, and drain-induced barrier lowering (DIBL) in sub-100nm transistors.

Why Tilt Implant Is Used

- Vertical (0°) implant: Dopants land directly below beam direction — cannot reach under gate overhang.
- Tilt implant: Ion beam enters at an angle → some ions pass beneath the gate edge → reach channel region under the spacer.
- Applications requiring tilt:
- Halo/pocket implants: P-type dopant angled under gate edges for NMOS → raises VT locally near channel ends → suppresses short-channel effects.
- LDD extension: Light tilt ensures S/D extension junction is self-aligned to gate edge with controlled lateral straggle.
- Well engineering: Retrograde well profile formed by high-energy angled implant.

Halo Pocket Implant

- Purpose: Counter-dope channel edges near S/D with opposite polarity → raise VT near channel pinch-off points → reduce DIBL.
- NMOS halo: B or BF₂ at 7–30° tilt → p-type halo pockets just under gate edge → VT raised near source and drain.
- PMOS halo: As or P at tilt → n-type halos → same effect.
- Rotation: 4-rotation implant (0°, 90°, 180°, 270°) → symmetric halos on all four sides of gate (especially important for 2D gates).
- Impact: Can reduce DIBL from 100 mV/V to <30 mV/V for a given gate length.

Implant Tilt Angle Effects

| Tilt Angle | Shadow Under Gate | Lateral Straggle | Use |
|-----------|-----------------|-----------------|-----|
| 0° | None | Vertical only | Source/drain, deep implants |
| 7° | Small | Small | LDD extension |
| 15–25° | Moderate | Moderate | Halo pocket |
| 30–45° | Large | Large | Well punch-through stop |

Process Considerations for Tilt Implant

- Shadowing: At high tilt angles, gate electrode shadows the implant on one side → asymmetric halos → needs multi-rotation.
- Pattern dependency: Nearby structures can shadow implant in dense arrays → layout-dependent VT variation.
- Dose correction: At tilt angle θ, effective dose on vertical surface = D × cos(θ) → must adjust dose for equivalent horizontal dose.
- Wafer rotation: Mechanical rotation of wafer between implant passes → 2-rotation (symmetric S/D direction), 4-rotation (all directions), or continuous rotation.

Tilt Implant in FinFET

- FinFETs have 3D fins → tilt implant geometry changes dramatically:
- Fin sidewalls need different tilt angles than fin tops.
- Shadowing from adjacent fins in dense arrays → halo under-dose on shielded sides.
- Effective tilt implant into fin sidewalls at 45–90° from wafer normal required.
- Alternative: Anti-punch-through (APT) vertical implant into fin bottom before fin formation — eliminates tilt shadow issue.

LDD Extension Tilt

- NMOS LDD: P → AsH₃ or PH₃, 7° tilt, low energy (1–10 keV) → shallow junction just under spacer.
- Tilt ensures extension aligns self-consistently to gate edge → controlled overlap capacitance.
- At 28nm: Extension junction depth Xj ~ 8–12 nm → tilt angle chosen to minimize Xj while maintaining lateral overlap.

Boron Channeling and Tilt

- B along <100> crystal direction → channels deep if 0° implant and wafer aligned.
- Tilt to 7° off major crystal axis → breaks channeling → more reproducible junction depth.
- BF₂ alternative: Heavier molecular ion → inherently less channeling, even at low tilt.

Angled tilt implantation is the three-dimensional dopant engineering tool that allows transistor designers to sculpt charge distributions in regions inaccessible to vertical beams — by directing ions beneath gate overhangs to create halo pockets, control channel profiles, and suppress short-channel effects, tilt implant has been essential to maintaining electrostatic transistor control as gate lengths scaled from 250nm to 20nm over three decades of CMOS development.

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