Antenna Effect is a plasma process-induced gate oxide damage mechanism where long metal wires accumulate charge during plasma etching — acting as "antennas" that collect plasma charges and force current through the thin gate oxide of connected transistors.

Mechanism

1. During plasma etch (or metal deposition), wafer surface collects charge from plasma. 2. Charge accumulates on metal conductor being etched. 3. If the only path for charge discharge is through a gate oxide: $V_{gate} = Q_{antenna} / C_{ox}$. 4. If $V_{gate} > V_{TDDB}$: Gate oxide damage occurs — trapped charges, increased leakage, accelerated TDDB.

Antenna Ratio

$$AR = \frac{\text{Metal area (connected to gate)}}{\text{Gate oxide area (driven by metal)}}$$

• Foundry rule: AR < 400 (metal), AR < 200 (via+metal combined).
• Larger metal area = more charge collection = larger antenna = more damage risk.

EDA Tool Antenna Checking

• DRC antenna rule check: CAD tools calculate AR for every gate input.
• Reports all antenna violations with AR and location.
• Checked at every metal layer independently and cumulatively.

Fixing Antenna Violations

Option 1 — Antenna Diode:

• Insert reverse-biased diode at the gate input pin.
• Diode clamps voltage: Any charge accumulated on metal → discharged through diode to supply/ground.
• Diode adds capacitance → slight delay penalty.
• Preferred fix: No timing impact for non-critical paths.

Option 2 — Wire Jumper (Layer Hopping):

• Route offending long wire to a higher metal layer (accumulates charge only on upper layers, not lower partial wires).
• Higher layers completed later in process → less plasma exposure time.
• No area cost but requires routing resource on upper layer.

Option 3 — Buffer Insertion:

• Insert a buffer in the middle of the long wire — breaks antenna connection.
• Buffer output drives the remaining net length.
• Cost: Extra cell, extra power, extra delay.

Antenna effect management is a critical DRC sign-off requirement — failing to fix antenna violations risks oxide damage that causes parametric drift and early-life failures in the field, particularly in IO and clock network paths with long metal wires.