ATPG (Automatic Test Pattern Generation) is the EDA process of automatically creating test patterns that detect manufacturing defects in digital circuits — targeting specific fault models to achieve high coverage while minimizing test time and pattern count.

Fault Models

• Stuck-At-0 (SA0): A node is permanently stuck at logic 0 regardless of input.
• Stuck-At-1 (SA1): A node is permanently stuck at logic 1.
• Transition Fault: A node fails to transition (slow-to-rise or slow-to-fall) — detects delay defects.
• Bridging Fault: Two nets shorted together.
• Open Fault: Broken connection — node floating.
• Path Delay Fault: Entire path from FF to FF is too slow (detects process-induced delay defects).

ATPG Algorithm

1. Fault Selection: Choose undetected fault. 2. Justification: Find input assignment that creates the fault effect at the faulty gate. 3. Propagation: Sensitize a path from fault location to a scannable output (scan FF or primary output). 4. Backtrack: If justification/propagation fail, try alternative paths. 5. Pattern Compaction: Merge multiple single-fault patterns into one (ATPG target: detect multiple faults per pattern).

Fault Coverage Formula

$$FC = \frac{\text{Detected Faults}}{\text{Total Testable Faults}} \times 100\%$$

• Target: > 98% SA0/SA1, > 95% transition fault for automotive/high-reliability.
• Consumer: > 95% SA0/SA1 acceptable.

ATPG Challenges

• Redundant Faults: Logically untestable (circuit is correct even with fault) — excluded from coverage denominator.
• ATPG Abort: ATPG times out before finding pattern for fault — reported as "undetectable."
• Clock domain crossings: Multi-cycle paths limit ATPG effectiveness.

DFT Enhancement for ATPG

• Scan insertion: Enables internal observability/controllability.
• Test point insertion: Add muxes or observe points to improve ATPG coverage in hard-to-test cones.
• Compression: ATPG generates patterns for internal chains; compressor maps to external channels.

Tools

• Synopsys TetraMAX (now DFTMAX Ultra).
• Siemens EDA (Mentor) Tessent FastScan.
• Cadence Modus.

ATPG is the scientific engine behind semiconductor quality — high ATPG fault coverage directly correlates with lower field defect rates, and every 1% of fault coverage improvement translates to measurable improvement in delivered product quality (DPPM reduction).