Backside Power Delivery (BSPDN) is an advanced integration architecture that delivers power from the back side of the wafer — separating signal routing (front side BEOL) from power distribution (back side) to independently optimize both, dramatically reducing IR drop and freeing signal routing resources.

BSPDN Integration

• TSV-like Nano-Through-Silicon Vias (nTSVs): Vertical connections from backside power network to front-side devices.
• Wafer Thinning: Thin the wafer to ~500 nm to expose nTSVs from the back side.
• Backside Metal: Build 2-4 metal layers on the wafer back side for power distribution.
• Bonding: Bond the thinned wafer to a carrier for mechanical support.

Why It Matters

• 50% IR Drop Reduction: Backside power delivery provides shorter, wider power paths directly to transistors.
• Signal Quality: Removing power from front-side BEOL reduces congestion and capacitive coupling.
• IMEC/Intel: Both have demonstrated BSPDN as a key enabler for sub-2nm technology nodes.

BSPDN is powering chips from below — a revolutionary approach that delivers power from the wafer back side while signals flow above.