Backside Power Delivery Network (BSPDN) is the revolutionary chip architecture that routes power supply (VDD/VSS) connections through the wafer backside instead of through the frontside metal stack — eliminating the 20-30% of frontside routing resources consumed by power wiring, reducing IR-drop by 30-50%, and enabling tighter standard cell heights by removing the buried power rail from the frontside, representing the most significant change to chip architecture since the introduction of copper interconnects.

Why Frontside Power Delivery Is Running Out of Room

In conventional chips, power (VDD, VSS) and signal wires share the same frontside BEOL metal stack. As standard cell heights shrink to 5-6 track pitches at 2nm and below, the metal routing congestion becomes extreme — power rails consume two of the five available tracks in each cell row, leaving only three for signal routing. This creates a routing bottleneck that limits effective gate density regardless of how small the transistors are.

BSPDN Architecture

The power delivery network is split between the two wafer sides:

• Frontside: Signal-only routing. All M0-Mx metal layers carry exclusively signal wires, maximizing routing density and reducing wire congestion.
• Backside: Power-only routing. A dedicated power delivery metal stack on the thinned wafer backside connects to the transistors through nano-TSVs that penetrate the ~500 nm of silicon between the backside metal and the frontside device layer.

Fabrication Flow

1. Frontside Fabrication: Standard FEOL and BEOL processing on the wafer frontside, including transistors and signal routing. 2. Wafer Bonding: The completed frontside is bonded face-down to a carrier wafer using oxide-oxide or hybrid bonding. 3. Substrate Thinning: The original wafer substrate is thinned from 775 um to ~500 nm, exposing the bottom of the active device layer (below the STI and source/drain regions). 4. Nano-TSV Formation: Small vias (~50-100 nm diameter) are etched through the remaining thin silicon to contact the frontside source/drain or power rail landing pads. 5. Backside Metal Deposition: 2-3 metal layers are deposited on the backside, forming the power grid (wide, low-resistance power lines optimized for current carrying, not density). 6. Backside Bumping: Power bumps on the backside connect directly to the package power distribution.

Benefits

Industry Adoption

Intel 18A (PowerVia) is the first production technology to implement BSPDN, with initial production in 2025. TSMC's N2P (2nm+) includes a backside power delivery option. Samsung and IMEC have demonstrated BSPDN research vehicles.

Backside Power Delivery is the architectural revolution that untangles the power-signal routing knot — giving each side of the wafer a dedicated job and unlocking standard cell density improvements that no amount of transistor shrinking alone could achieve.