Backside Power Delivery Network (BSPDN) is an advanced chip architecture that routes power supply lines through the backside of the silicon wafer rather than through the traditional frontside BEOL metal stack, freeing frontside routing resources for signal interconnects and dramatically reducing IR drop and power delivery impedance — representing a paradigm shift in CMOS process integration that requires wafer thinning, backside patterning, and through-silicon connections.

• Motivation: In conventional designs, power and signal wires share the same BEOL metal layers, creating congestion that limits routing density and forces wide power rails that consume valuable wiring tracks; moving power to the backside eliminates this competition, enabling 20-30 percent improvement in standard cell utilization and significant IR drop reduction.
• Process Flow Overview: Transistors and frontside BEOL are fabricated on the wafer front; the wafer is then bonded face-down to a carrier, thinned from the backside to expose buried power rails or nano-through-silicon-vias (nTSVs), and backside metal layers are patterned to form the power distribution network.
• Wafer Thinning: The silicon substrate is thinned from the original 775 micrometers to approximately 500 nm or less using a combination of mechanical grinding, CMP, and selective etch; precise thickness control and etch stops (such as an epitaxial layer or buried oxide in SOI) ensure the backside surface is uniform and damage-free.
• Buried Power Rail (BPR): Power rails are embedded in shallow trenches below the transistor active region during front-end processing; these rails are later exposed from the backside and connected to the backside power network, providing a low-resistance path that does not compete with signal routing.
• Nano-TSV Formation: High-aspect-ratio vias with diameters of 50-200 nm are etched from the backside through the thinned silicon to contact the buried power rails or frontside metal levels; ALD barrier and seed deposition followed by bottom-up metal fill creates reliable vertical connections.
• Backside Metallization: After nTSV formation, one or more metal layers are patterned on the wafer backside using standard damascene or subtractive patterning; these layers distribute VDD and VSS across the chip with wide, low-resistance power meshes that do not face the pitch constraints of the frontside BEOL.
• Carrier Bonding and Debonding: Temporary bonding materials must withstand all backside processing temperatures while enabling clean debonding without damaging the fragile thinned wafer; adhesive bonding with laser or thermal debonding is the most common approach.
• Thermal Management: Removing the bulk silicon reduces the thermal mass and changes the heat dissipation path; backside metallization can serve dual duty as both power distribution and thermal spreader, and thermal vias may be added to enhance heat extraction. BSPDN is actively being developed for production at the 2 nm node and beyond, as it fundamentally resolves the power delivery bottleneck that has constrained chip performance scaling in conventional architectures.