Backside Power Delivery Network (BSPDN) is the semiconductor manufacturing innovation that moves the power supply wiring from the front side of the chip (where it competes for routing space with signal interconnects) to the back side of the silicon die — using through-silicon nanovias to deliver VDD and VSS directly to transistors from behind, freeing 20-30% more front-side routing tracks for signals and reducing IR drop by 30-50% compared to conventional front-side power delivery.

The Power Delivery Problem

In conventional chips, power (VDD/VSS) and signal wires share the same BEOL metal stack. The lowest metal layers (M1-M3) are dense with signal routing and local power rails. Voltage must traverse 10-15 metal layers from the top-level power bumps down to the transistors, accumulating IR drop. As supply voltages decrease (0.65-0.75 V at advanced nodes), even small IR drop (30-50 mV) causes timing violations and performance loss.

BSPDN Architecture

1. Front Side: Only signal interconnects in the BEOL stack. No power rails consuming M1-M3 routing resources. 2. Buried Power Rail (BPR): A power rail (VDD or VSS) embedded below the transistor level, within the shallow trench isolation (STI) or below the active device layer. Provides the local power connection point. 3. Backside Via (Nanovia): After front-side BEOL fabrication, the wafer is flipped and thinned to ~500 nm-1 μm from the backside. Nano-scale vias are etched from the backside to contact the BPR. 4. Backside Metal (BSM): 1-3 layers of thick metal (Cu or Ru) on the backside carry power from backside bumps to the nanovias/BPR. 5. Backside Power Bumps: Power delivery connections (C4 bumps or hybrid bonds) on the back of the die connect to the package power planes.

Benefits

• Signal Routing: 20-30% more M1-M3 tracks available for signal routing → higher logic density or relaxed routing congestion.
• IR Drop: Power delivery path is dramatically shortened (backside metal → nanovia → BPR → transistor vs. frontside bump → M15 → M14 → ... → M1 → transistor). IR drop reduction: 30-50%.
• Cell Height Scaling: Removing power rails from the standard cell enables smaller cell heights (5T → 4.3T track heights), increasing transistor density.
• Decoupling Capacitor Access: Backside metal planes act as large parallel-plate capacitors, improving power integrity.

Manufacturing Challenges

• Wafer Thinning: The silicon substrate must be thinned to ~500 nm from the backside to expose the buried power rail — extreme thinning on a carrier wafer with nm-precision endpoint.
• Nanovia Alignment: Backside-to-frontside alignment accuracy must be <5 nm to hit BPR contacts — pushing the limits of backside lithography.
• Thermal Management: Removing the silicon substrate on the backside eliminates the traditional heat dissipation path through the die backside. Alternative thermal solutions (backside thermal vias, advanced TIM) are required.

Industry Adoption

• Intel PowerVia: First announced for Intel 20A node (2024). Intel demonstrated a fully functional backside power test chip (2023) showing improved performance and power delivery.
• TSMC N2P (2nm+): BSPDN planned for second-generation 2 nm (2026-2027).
• Samsung SF2: Backside power delivery for 2 nm GAA node.

BSPDN is the power delivery revolution that reorganizes chip architecture from a shared front-side into a dedicated dual-side structure — giving signal routing and power delivery each their own optimized metal stack, solving the voltage drop and routing congestion problems that increasingly constrained single-side chip designs.