Backside Power Delivery Network (BSPDN) is the revolutionary interconnect architecture that moves the entire power distribution network from the front side of the wafer (where it competes for routing resources with signal wires) to the backside — delivering power through the silicon substrate via nano-TSVs directly to transistor rails, simultaneously freeing 20-30% of front-side metal layers for signal routing and reducing IR drop by 2-3x through shorter, wider power paths.

The Problem BSPDN Solves

In conventional front-side power delivery, power rails share the lower metal layers (M0-M2) with dense signal routing. As transistors shrink below 3nm, the conflict worsens: power rails consume routing tracks that signal nets desperately need, while the resistance of thin, narrow power wires creates IR drop that steals voltage margin from shrinking supply voltages (0.5-0.7V). Every millivolt of IR drop directly reduces transistor switching speed.

BSPDN Process Flow

1. Front-Side Fabrication: Complete transistor formation (FEOL) and signal interconnect layers (BEOL) using standard processing on the wafer front side. 2. Carrier Wafer Bonding: Bond the front side to a carrier wafer using dielectric-to-dielectric bonding. 3. Substrate Thinning: Grind and etch the original substrate from the backside, stopping at the buried oxide or etch-stop layer. The remaining silicon is only 300-500nm thick. 4. Nano-TSV Formation: Etch and fill through-silicon vias (50-100nm diameter) from the backside to connect to the transistor-level buried power rail (BPR). 5. Backside Metal Stack: Deposit 2-4 metal layers on the backside dedicated exclusively to power distribution — wide, thick lines with minimal resistance. 6. Backside Bumping: Form power delivery bumps/pads on the backside for connection to the package power grid.

Key Technical Challenges

• Nano-TSV Alignment: The TSVs must align to front-side BPRs with sub-10nm accuracy through the thinned substrate — demanding backside-to-frontside overlay metrology at extreme precision.
• Thermal Management: The thinned substrate and additional metal layers on the backside alter thermal dissipation paths. Heat must now flow through the backside metal stack or laterally through the thinned silicon.
• Substrate Thinning Uniformity: Non-uniform thinning creates TSV depth variation, affecting contact resistance. Atomic layer etching and CMP techniques achieve sub-5nm thickness uniformity.
• Process Temperature Budget: Backside metal deposition must not damage front-side transistors or interconnects — temperatures must stay below 400°C.

Industry Adoption

Intel introduced BSPDN (called PowerVia) at the Intel 20A node (2024). Samsung and TSMC are developing their own BSPDN implementations for sub-2nm nodes. The technology is considered essential for continued logic scaling — without it, the front-side routing congestion at gate-all-around dimensions makes standard cell utilization impractical.

BSPDN is the architectural paradigm shift that decouples power delivery from signal routing — solving two problems simultaneously by giving power its own dedicated infrastructure on the wafer backside, enabling the continued scaling of both transistor density and interconnect performance beyond the 2nm node.