BEOL (Back End of Line) is the interconnect stack built above the transistors that wires everything together — consisting of multiple metal layers (copper, cobalt, tungsten), vias, low-k dielectrics, and passivation that route electrical signals, deliver power, and connect billions of transistors into a functioning integrated circuit.

What Is BEOL?

• Definition: The second major phase of semiconductor manufacturing, covering all metal interconnect layers built on top of the FEOL transistors — from the first metal layer (M1) through the top metal and passivation.
• Layer Count: Modern chips have 10-15+ metal layers at leading-edge nodes (Apple M-series has 13 metal layers).
• Materials: Copper (bulk metal layers), cobalt (lower metal layers at advanced nodes), tungsten (contacts/vias), and low-k dielectrics (SiCOH, k < 3.0).

Why BEOL Matters

• Signal Routing: Trillions of interconnections must be routed across the chip — BEOL is essentially a massive 3D wiring network.
• RC Delay Dominance: At advanced nodes, interconnect delay (RC delay) exceeds transistor delay — BEOL is the bottleneck for chip performance.
• Power Delivery: Lower metal layers deliver current from power pads to billions of transistors — IR drop management is critical.
• Cost: BEOL processing accounts for 50-60% of total wafer processing cost and time at advanced nodes.

BEOL Metal Layer Hierarchy

• Local Interconnects (M1-M2): Finest pitch (20-30nm), connect adjacent transistors — use cobalt or ruthenium for resistance at small dimensions.
• Intermediate Metals (M3-M8): Medium pitch (40-100nm), route signals within logic blocks — copper with thin barrier layers.
• Semi-Global (M9-M11): Wider pitch (100-400nm), route signals between major blocks — copper with lower resistance.
• Global (M12+): Thickest metal layers (800nm-3µm), power distribution and long-distance routing — aluminum or thick copper.

Key BEOL Process Steps

• Dielectric Deposition: Low-k dielectric (k < 3.0-2.5) deposited between metal layers — reduces capacitance and RC delay.
• Lithography and Etch: Patterns trenches and via holes in the dielectric — dual-damascene process creates both simultaneously.
• Barrier/Seed Deposition: Thin TaN/Ta barrier prevents copper from diffusing into the dielectric; Cu seed enables electroplating.
• Copper Electroplating: Fills trenches and vias with copper from the bottom up — the primary metallization method since 130nm node.
• CMP (Chemical Mechanical Polishing): Removes excess copper and planarizes the surface for the next metal layer.
• Capping: Dielectric cap (SiCN) prevents copper oxidation and diffusion between layers.

BEOL Challenges at Advanced Nodes

BEOL Equipment Vendors

• Deposition: Applied Materials (Endura, Producer), Lam Research (ALTUS), ASM — metal and dielectric deposition.
• Etch: Lam Research (Kiyo, Flex), Tokyo Electron — dielectric and metal etch.
• CMP: Applied Materials (Reflexion), Ebara — copper and dielectric planarization.
• Plating: Lam Research (Sabre), Applied Materials (Raider) — copper electroplating.
• Metrology: KLA, Onto Innovation — thickness, resistance, and defect inspection.

BEOL is the critical wiring backbone that transforms isolated transistors into integrated circuits — and as transistor scaling slows, BEOL innovation through new materials, lower-k dielectrics, and backside power delivery is becoming the primary driver of chip performance improvement.