BEOL (Back End of Line) — the portion of chip fabrication that creates the multilayer metal interconnect stack connecting transistors to each other and to I/O pads, after transistor formation is complete.

What BEOL Includes

• Contact/via layers: Connecting transistors to first metal
• Metal layers (M1 through M10–M15): Copper wires of increasing pitch
• Inter-metal dielectrics (low-k materials)
• Passivation and pad formation

BEOL Layer Structure

<svg viewBox="0 0 536 169" xmlns="http://www.w3.org/2000/svg" style="max-width:100%;height:auto" role="img"><rect x="0" y="0" width="536" height="169" rx="12" fill="#0d1117"/><g font-family="ui-monospace,SFMono-Regular,Menlo,Consolas,&quot;Liberation Mono&quot;,monospace" font-size="14"><text xml:space="preserve" x="20" y="31.7"><tspan fill="#c9d1d9">Passivation + Bond Pads</tspan></text><text xml:space="preserve" x="20" y="50.7"><tspan fill="#6e7681">├──</tspan><tspan fill="#c9d1d9"> Thick metal (redistribution, power)</tspan></text><text xml:space="preserve" x="20" y="69.7"><tspan fill="#6e7681">├──</tspan><tspan fill="#c9d1d9"> Global wires (M8-M12): Wide, thick — power/ground/clock</tspan></text><text xml:space="preserve" x="20" y="88.7"><tspan fill="#6e7681">├──</tspan><tspan fill="#c9d1d9"> Intermediate wires (M4-M7): Medium pitch</tspan></text><text xml:space="preserve" x="20" y="107.7"><tspan fill="#6e7681">├──</tspan><tspan fill="#c9d1d9"> Local wires (M1-M3): Tightest pitch, shortest wires</tspan></text><text xml:space="preserve" x="20" y="126.7"><tspan fill="#6e7681">└──</tspan><tspan fill="#c9d1d9"> Contacts (MOL: Middle-of-Line)</tspan></text><text xml:space="preserve" x="20" y="145.7"><tspan fill="#c9d1d9">    </tspan><tspan fill="#6e7681">└──</tspan><tspan fill="#c9d1d9"> FEOL: Transistors</tspan></text></g></svg>

Key BEOL Processes

• Dual damascene copper metallization
• Low-k dielectric deposition and curing
• CMP at every metal level
• Barrier/seed deposition (PVD)
• Electroplating (ECD)

BEOL Scaling Challenge

• Wire resistance increases as pitch shrinks (surface/grain boundary scattering)
• RC delay of wires now dominates over transistor delay
• BEOL contributes 50–70% of total chip delay at advanced nodes

BEOL accounts for ~60% of all fabrication process steps and is increasingly the performance bottleneck — interconnect innovation is as critical as transistor innovation.