BIST (Built-In Self-Test) is an on-chip testing architecture where the IC contains its own test pattern generator and response analyzer, enabling the chip to test itself without relying entirely on external test equipment. BIST is a key Design for Test (DFT) technique that reduces test cost and improves test coverage.

How BIST Works

• Pattern Generation: An on-chip Linear Feedback Shift Register (LFSR) or similar circuit generates pseudo-random test patterns applied to the logic or memory under test.
• Response Compaction: Output responses are compressed using a Multiple Input Signature Register (MISR) into a compact signature that is compared against a known-good reference.
• Pass/Fail Decision: If the final signature matches the expected value, the circuit passes. Any manufacturing defect that causes a different output will alter the signature.

Types of BIST

• Logic BIST (LBIST): Tests combinational and sequential logic blocks. Commonly used with scan chains for comprehensive coverage.
• Memory BIST (MBIST): Specifically targets embedded SRAM, ROM, register files, and CAMs with specialized algorithms like March C- and checkerboard patterns.
• Analog BIST: Emerging technique for testing analog/mixed-signal circuits on-chip.

Advantages

• Reduced ATE Dependence: Less reliance on expensive external testers since the chip runs its own tests.
• At-Speed Testing: BIST runs at the chip's actual operating frequency, catching timing-related defects.
• Field Testing: BIST can be triggered in the field for periodic health checks and diagnostics.

Trade-Off: BIST adds silicon area overhead (typically 1–5%), but the savings in test time and equipment cost make it worthwhile for most production devices.