Home Knowledge Base Boron-Doped SiGe (B:SiGe) for PMOS Source/Drain

Boron-Doped SiGe (B:SiGe) for PMOS Source/Drain is the in-situ doped epitaxial material grown in the source/drain regions of PMOS transistors that simultaneously provides compressive channel strain for hole mobility enhancement and heavy boron doping for low contact resistance — where the germanium concentration (25-60 at%), boron doping level (1-5 × 10²⁰/cm³), and epitaxial layer geometry are precisely engineered to maximize PMOS drive current while maintaining crystal quality and avoiding relaxation defects.

Why B:SiGe for PMOS

B:SiGe S/D Process Flow

1. S/D recess etch: Remove Si from S/D regions (typically 30-60nm deep). 2. Pre-epitaxy clean: HF + H₂ bake → remove native oxide from recess. 3. SiGe nucleation: Thin undoped SiGe buffer → smooth interface. 4. B:SiGe growth: Main stressor layer with target Ge% and B doping. 5. Optional Si cap: Thin Si layer for silicide contact formation.

Ge Content and Strain

Ge ContentLattice MismatchChannel StrainMobility GainRisk
25%1.0%Moderate~25%Low
35%1.4%High~40%Medium
45%1.8%Very high~55%Higher
60%2.5%Maximum~70%Relaxation risk

Boron Doping

Epitaxy Challenges

ChallengeCauseMitigation
RelaxationExceeding critical thickness at high Ge%Multi-step Ge grading
DislocationsLattice mismatch strain reliefOptimize recess geometry
Ge non-uniformityGas depletion, loading effectsMulti-zone gas delivery
FacetingCrystal-orientation-dependent growthTemperature/pressure tuning
Boron out-diffusionLater thermal steps diffuse BMinimize thermal budget
Pattern-dependent growthDense vs. isolated features grow differentlyDummy pattern insertion

FinFET/GAA Specific Considerations

Boron-doped SiGe source/drain epitaxy is the single most impactful PMOS performance enhancement in modern CMOS technology — by combining strain engineering (Ge content), doping engineering (in-situ B), and geometric optimization (recess depth and shape) in one process step, B:SiGe S/D delivers the 40-60% PMOS mobility improvement that closes the gap with NMOS performance and enables the balanced circuit speeds required for competitive logic products at every node from 22nm through 2nm and beyond.

boron doped sigeb sige source drainpmos source drain epitaxysige sd stressorpmos epi

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