Bottom Dielectric Isolation

# Bottom Dielectric Isolation (BDI) in Gate-All-Around (GAA) Nanosheets

In Gate-All-Around (GAA) nanosheets and complementary field-effect transistors (CFET) at the 3 nm, 2 nm, and sub-2 nm nodes, Bottom Dielectric Isolation (BDI) is the front-end-of-line (FEOL) integration architecture that places a self-aligned, highly insulating dielectric layer ( $\text{SiO}_2$ or $\text{SiN}$ , thickness $t_{BDI} \approx 10\text{ to }15\,\text{nm}$ ) directly beneath the bottom nanosheet channel and the source/drain ( $$S/D$$ ) epitaxy.

In conventional bulk-silicon FinFETs and early GAA prototypes, the transistor channel stack is fabricated directly on top of the crystalline silicon substrate. While the gate wrap-around electrode provides electrostatic control over the elevated silicon nanosheet ribbons, the un-gated bulk silicon directly beneath the bottom channel remains vulnerable to drain-to-source electric field penetration. Under applied drain bias ( $V_{DS} = V_{DD}$ ), severe Drain-Induced Barrier Lowering (DIBL) in the un-gated substrate triggers massive sub-channel punch-through leakage ( $I_{leak,sub-fin}$ ), accounting for $30\%\text{ to }50\%$ of the transistor total off-state leakage current ( $I_{off}$ ). By physically cutting off the parasitic substrate conduction path, Bottom Dielectric Isolation suppresses off-state leakage by up to $10\times$ , eliminates sub-fin junction capacitance, and provides the baseline physical barrier required for Backside Power Delivery Networks (BSPDN).

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## 1. Physical Mechanisms of Sub-Channel Punch-Through Leakage

In a nanoscale transistor fabricated on bulk silicon, the depletion regions formed around the reverse-biased source and drain pn-junctions extend deeply into the underlying substrate. When the channel length ( $$L_g$$ ) shrinks below $18\,\text{nm}$ , the depletion regions of the source and drain merge beneath the gate electrode, a phenomenon known as punch-through.

### 1.1 Mathematical Formulation of Sub-Fin Leakage
In a conventional bulk GAA nanosheet without BDI, the total off-state leakage current measured between source and drain ( $I_{off,total}$ ) is the superposition of the active nanosheet channel subthreshold conduction and the parasitic bulk sub-channel current:

I_{off,total} = I_{subthreshold,channels} + I_{leak,sub-fin}

The parasitic sub-fin current $I_{leak,sub-fin}$ flows through the un-gated silicon volume beneath the bottom nanosheet:

I_{leak,sub-fin} = q \cdot D_n \cdot \frac{n_i^2}{N_{well}} \cdot \frac{A_{sub}}{L_{eff,sub}} \cdot \exp\left( \frac{q \cdot (\Delta \Phi_{B0} - \text{DIBL}_{sub} \cdot V_{DS})}{\eta_{sub} \cdot k_B T} \right)

Where:
- $q = 1.602 \times 10^{-19}\,\text{C}$ is the elementary electron charge.
- $$D_n$$ is the electron diffusion coefficient in silicon.
- $$n_i$$ is the intrinsic carrier concentration of silicon ( $1.0 \times 10^{10}\,\text{cm}^{-3}$ at $300\,\text{K}$ ).
- $N_{well}$ is the substrate p-well active dopant concentration ( $\approx 10^{18}\,\text{cm}^{-3}$ ).
- $A_{sub} = W_{fin} \cdot H_{sub}$ is the cross-sectional area of the un-gated sub-channel conduction path.
- $L_{eff,sub}$ is the effective electrical path length between source and drain through the bulk.
- $\Delta \Phi_{B0}$ is the zero-bias electrostatic potential barrier height between the source junction and the substrate.
- $\text{DIBL}_{sub}$ is the drain-induced barrier lowering coefficient of the bulk substrate.
- $\eta_{sub}$ is the subthreshold ideality factor of the substrate, typically very poor ( $\eta_{sub} \ge 2.5\text{ to }3.5$ ) because the gate electrode cannot wrap beneath the bulk fin.

As $V_{DS}$ is raised to the supply voltage ( $V_{DD} \approx 0.7\text{ to }0.8\,\text{V}$ ), $\text{DIBL}_{sub} \cdot V_{DS}$ severely suppresses the potential barrier $\Delta \Phi_B$ , allowing exponential electron injection from source to drain directly through the substrate. In leading-edge $3\,\text{nm}$ logic, this parasitic leakage accounts for $35\%\text{ to }50\%$ of the entire chip off-state standby power.

### 1.2 Extinction via Dielectric Barrier
When a Bottom Dielectric Isolation layer with thickness $t_{BDI} \ge 10\,\text{nm}$ and dielectric constant $\kappa_{BDI} \approx 3.9$ ( $\text{SiO}_2$ ) or $\kappa_{BDI} \approx 7.0$ ( $\text{SiN}$ ) is inserted, the physical boundary conditions for carrier transport are transformed:

A_{sub} \to 0 \implies I_{leak,sub-fin} = 0

The active transistor is completely decoupled from the bulk substrate, effectively converting the bulk silicon wafer into a localized Silicon-on-Insulator (SOI) architecture without the severe cost, thermal dissipation, and floating-body penalties of traditional SOI wafers.

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## 2. Quantitative Modeling: Electrical Transfer Characteristics & Capacitance

### 2.1 Junction Capacitance Sashing
In bulk CMOS, the depletion capacitance between the source/drain heavily doped regions ( $N_D \approx 3 \times 10^{20}\,\text{cm}^{-3}$ ) and the substrate ( $N_A \approx 10^{18}\,\text{cm}^{-3}$ ) is given by:

C_{j,bulk} = \frac{\epsilon_0 \cdot \epsilon_{Si}}{W_{dep}} \cdot A_{junction} = \sqrt{\frac{q \cdot \epsilon_0 \epsilon_{Si} N_A}{2 (V_{bi} + V_R)}} \cdot A_{junction}

Where $\epsilon_{Si} = 11.7$ and $W_{dep}$ is the depletion width ( $\approx 25\text{ to }35\,\text{nm}$ ). In modern compact standard cells, $C_{j,bulk}$ contributes up to $25\%$ of the total load capacitance seen by driving logic stages.

When replaced by Bottom Dielectric Isolation ( $\text{SiO}_2$ , $t_{BDI} = 12\,\text{nm}$ , $\epsilon_{ox} = 3.9$ ):

C_{BDI} = \frac{\epsilon_0 \cdot \epsilon_{ox}}{t_{BDI}} \cdot A_{junction}

Because the dielectric constant of silicon dioxide is only one-third that of silicon ( $\epsilon_{ox} / \epsilon_{Si} \approx 3.9 / 11.7 = 0.333$ ), the bottom parasitic capacitance is slashed by:

\frac{C_{BDI}}{C_{j,bulk}} \approx \frac{\epsilon_{ox}}{\epsilon_{Si}} \cdot \frac{W_{dep}}{t_{BDI}} \approx 0.333 \cdot \frac{30\,\text{nm}}{12\,\text{nm}} \approx 0.83

However, because the source/drain junction is bounded by oxide instead of high-permittivity silicon on three sides (STI + Inner Spacer + BDI), the total parasitic junction charge storage drops by $>60\%$ , driving an overall transistor input capacitance reduction of $\approx 25\%$ and reducing gate switching propagation delay ( $\tau = R_{on} \cdot C_{total}$ ).

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## 3. Integration Methodologies: Full-BDI vs. S/D-Only BDI

Leading semiconductor foundries implement two primary process integration flows to create Bottom Dielectric Isolation:

+----------------------------------------------------------------------------------------------------+
|                               BDI INTEGRATION ARCHITECTURE COMPARISON                              |
+----------------------+-------------------------------------+---------------------------------------+
| PARAMETER            | FULL BOTTOM DIELECTRIC ISOLATION    | SOURCE / DRAIN-ONLY BDI (PUNCHED BDI) |
+----------------------+-------------------------------------+---------------------------------------+
| Dielectric Coverage  | Continuous dielectric barrier under | Dielectric plugs strictly localized   |
|                      | channel and source/drain regions    | beneath epitaxial source/drain pads   |
+----------------------+-------------------------------------+---------------------------------------+
| Formation Mechanism  | Thermal selective oxidation of a    | Anisotropic bottom recess etch during |
|                      | sacrificial Si₀.₅Ge₀.₅ base layer   | S/D cavity etch followed by ALD fill  |
+----------------------+-------------------------------------+---------------------------------------+
| Sub-Channel Leakage  | Completely zero (100% extinguished) | Extremely low (>90% suppressed)       |
+----------------------+-------------------------------------+---------------------------------------+
| Channel Self-Heating | Higher thermal boundary resistance; | Superior heat dissipation through     |
| Sensitivity          | relies on HKMG heat conduit         | sub-gate silicon into bulk substrate  |
+----------------------+-------------------------------------+---------------------------------------+
| Process Complexity   | Very high (Narrow thermal oxidation | High (Self-aligned dry etch and       |
|                      | selectivity window vs. Si channel)  | selective dielectric pull-back)       |
+----------------------+-------------------------------------+---------------------------------------+
| Backside Power Rail  | Ideal etch-stop for backside deep   | Requires additional etch-stop layer   |
| Compatibility        | contact via (TSV) etching           | for backside contact alignment        |
+----------------------+-------------------------------------+---------------------------------------+
| High-Volume Status   | Intel 18A / TSMC A16 Target         | Production in Samsung SF3 / TSMC N2   |
+----------------------+-------------------------------------+---------------------------------------+

### 3.1 Selective Oxidation of High-Ge Sacrificial Base Layer
In the Full-BDI approach, the epitaxy engineer inserts an extra sacrificial layer at the very base of the superlattice with a substantially higher germanium content than the inter-sheet sacrificial layers:
- Channel sacrificial layers: $\text{Si}_{0.75}\text{Ge}_{0.25}$ ( $25\%\,\text{Ge}$ , $t_{sac} \approx 10\,\text{nm}$ )
- Bottom BDI sacrificial layer: $\text{Si}_{0.50}\text{Ge}_{0.50}$ ( $50\%\,\text{Ge}$ , $t_{BDI,sac} \approx 15\,\text{nm}$ )

Because the oxidation rate of $\text{SiGe}$ accelerates exponentially with germanium concentration due to the catalytic effect of germanium at the oxidizing interface:

\frac{ER_{ox}(\text{Si}_{0.5}\text{Ge}_{0.5})}{ER_{ox}(\text{Si}_{0.75}\text{Ge}_{0.25})} \approx 15:1

\frac{ER_{ox}(\text{Si}_{0.5}\text{Ge}_{0.5})}{ER_{ox}(\text{Si})} > 60:1

When exposed to low-temperature wet steam ( $\text{H}_2\text{O}$ vapor at $450^\circ\text{C}\text{ to }550^\circ\text{C}$ ), the bottom $\text{Si}_{0.5}\text{Ge}_{0.5}$ layer oxidizes laterally at high velocity, converting entirely into silicon dioxide ( $\text{SiO}_2$ ) while the upper $\text{Si}_{0.75}\text{Ge}_{0.25}$ layers and crystalline silicon nanosheet channels experience negligible oxidation. Concurrently, germanium atoms are rejected from the advancing oxide front and migrate harmlessly into underlying sinks, leaving a pure, defect-free $\text{SiO}_2$ dielectric sheet.

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## 4. Synergistic Co-Integration with Backside Power Delivery Networks (BSPDN)

The incorporation of Bottom Dielectric Isolation is a vital prerequisite for modern Backside Power Delivery Networks (BSPDN)—such as Intel PowerVia and TSMC Super Power Rail (SPR).

+----------------------------------------------------------------------------------------------------+
|                                    BDI & BSPDN INTEGRATION PHASES                                  |
+----------------------+-------------------------------------+---------------------------------------+
| PROCESS PHASE        | UNIT OPERATION                      | STRUCTURAL ROLE OF BDI                |
+----------------------+-------------------------------------+---------------------------------------+
| Frontside Processing | Nanosheet fabrication, BDI insertion| BDI encapsulates the transistor bottom|
|                      | and standard multi-layer metallization| and preserves strain in the channels  |
+----------------------+-------------------------------------+---------------------------------------+
| Carrier Wafer Bond   | Frontside oxide-oxide fusion bonding| Protects active device layer during   |
| & Wafer Thinning     | to handle wafer; backside CMP polish| mechanical grind down to ~500 nm      |
+----------------------+-------------------------------------+---------------------------------------+
| Extreme Silicon Thin | Wet chemical etch-stop on buried BDI| BDI acts as the crystalline etch-stop,|
| Down to Active Layer | oxide boundary (Selectivity > 500:1)| preventing over-etch into S/D epi     |
+----------------------+-------------------------------------+---------------------------------------+
| Backside Contact Via | Litho and dry etch through BDI to   | BDI ensures high-voltage insulation   |
| (Nano-TSV) Etch      | contact Source epitaxy directly     | between power via and adjacent silicon|
+----------------------+-------------------------------------+---------------------------------------+

Without BDI, thinning the wafer from the backside down to sub-micron thickness ( $t_{Si} < 50\,\text{nm}$ ) carries an extreme risk of punch-through variation and non-uniform contact resistance across the $300\,\text{mm}$ wafer. The uniform dielectric oxide of BDI provides a resilient, atomic-precision chemical and physical etch stop, enabling high-yield manufacturing of direct backside contact vias to source junctions.

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## 5. Technology Comparison: Substrate Isolation Evolution Across Nodes

+----------------------------------------------------------------------------------------------------+
|                               COMPARATIVE MATRIX OF SUBSTRATE ISOLATION                            |
+----------------------+---------------------+-----------------------+-------------------------------+
| PARAMETER            | 16nm / 7nm FINFET   | 3nm GAA (BULK)        | 2nm / A16 GAA & CFET (BDI)    |
+----------------------+---------------------+-----------------------+-------------------------------+
| Isolation Mechanism  | Deep Well Implants  | Punch-Through Stop    | Physical Bottom Dielectric    |
|                      | & Halo Doping       | Implants (PTSL)       | Isolation Layer (BDI)         |
+----------------------+---------------------+-----------------------+-------------------------------+
| Punch-Through Control| Fair (Heavily doped | Poor (Dopant diffusion| Absolute (Dielectric barrier  |
|                      | substrate junction) | shorts nanosheets)    | eliminates punch-through)     |
+----------------------+---------------------+-----------------------+-------------------------------+
| Off-State Leakage    | High substrate      | High (35–50% of I_off | Minimal (Sub-channel leakage  |
| Contribution         | leakage fraction    | in sub-fin path)      | suppressed by >90%)           |
+----------------------+---------------------+-----------------------+-------------------------------+
| Subthreshold Swing   | 68 to 72 mV/dec     | 70 to 76 mV/dec       | 62 to 65 mV/dec               |
| Degradation          | (Bulk loss)         | (Sub-fin degradation) | (Near theoretical limit)      |
+----------------------+---------------------+-----------------------+-------------------------------+
| Thermal Dissipation  | Excellent (Direct   | Excellent (Direct     | Moderate (Requires engineered |
|                      | thermal fin path)   | thermal fin path)     | metal gate heat sink paths)   |
+----------------------+---------------------+-----------------------+-------------------------------+
| Backside Power Rail  | Incompatible        | Very difficult        | Native compatibility          |
| Readiness            | (Shorts substrate)  | (Requires spacer stop)| (BDI acts as TSV etch-stop)   |
+----------------------+---------------------+-----------------------+-------------------------------+

Bottom Dielectric Isolation

Take bottom dielectric isolation further