Boundary scan is a testing technique defined by the IEEE 1149.1 (JTAG) standard that allows engineers to test the electrical connections between integrated circuits on a printed circuit board (PCB) without using physical test probes. It works by placing special test cells at every I/O pin of a JTAG-compliant chip.

How It Works

• Boundary Scan Cells: Each I/O pin has a dedicated test cell that can capture the current signal value or drive a specific value onto the pin, all controlled serially through the JTAG interface.
• Testing Interconnects: By driving known patterns from one chip's output pins and capturing them at another chip's input pins, engineers can detect open circuits, short circuits, stuck-at faults, and bridging defects in board-level wiring.
• Daisy Chain: Multiple JTAG devices on a board are connected in a serial chain (TDO to TDI), allowing a single JTAG controller to access all devices.

Key Benefits

• No Physical Probes Needed: Critical for modern PCBs with fine-pitch BGA packages and high-density routing where bed-of-nails fixtures cannot reach test points.
• Non-Intrusive: Testing happens through existing I/O pins without modifying the board design.
• Programmable: Test patterns can be updated in software without hardware changes.

Beyond Board Test

Boundary scan has expanded beyond its original scope to support in-system programming of flash and FPGAs, cluster testing of multiple boards, and integration with functional test environments. It remains essential for manufacturing test of complex electronic assemblies.