Boundary Scan and JTAG (IEEE 1149.1) is the standardized test access architecture that provides controllability and observability of chip I/O pins through a serial scan chain, enabling board-level interconnect testing, in-system programming, and debug access without requiring physical probes on individual pins — an indispensable infrastructure for manufacturing test and field diagnostics of complex multi-chip printed circuit boards.

JTAG Architecture:

• Test Access Port (TAP): four mandatory signals — TCK (test clock), TMS (test mode select), TDI (test data in), TDO (test data out) — plus optional TRST (test reset); the TAP controller is a 16-state finite state machine that sequences through test operations based on TMS transitions
• TAP Controller States: Idle, Select-DR-Scan, Capture-DR, Shift-DR, Update-DR for data register operations; parallel states for instruction register operations; the controller transitions deterministically based on TMS value at each TCK rising edge
• Instruction Register (IR): selects which test data register is connected between TDI and TDO; mandatory instructions include BYPASS (single-bit pass-through for chain shortening), EXTEST (drive/capture boundary scan cells), SAMPLE/PRELOAD (observe I/O without disturbing operation), and IDCODE (read 32-bit device identification)
• Data Registers: BYPASS register (1 bit), identification register (32 bits), and the boundary scan register (one cell per I/O pin); optional user-defined registers provide access to internal test structures, configuration memory, or debug logic

Boundary Scan Cell Design:

• Cell Architecture: each boundary scan cell contains a capture flip-flop, an update flip-flop, and a multiplexer; during normal operation the cell is transparent; during test mode the capture flop samples the pin state (observe) and the update flop drives a test value onto the pin (control)
• Cell Types: input cells observe signals coming into the chip; output cells can both observe and drive signals leaving the chip; bidirectional cells handle I/O pins with tristate control; cells for analog pins provide limited digital test access
• Scan Chain Formation: all boundary scan cells are connected in a serial shift register from TDI to TDO; the chain order is defined in the BSDL (Boundary Scan Description Language) file that accompanies each JTAG-compliant device
• BSDL File: standardized text description of each device's boundary scan implementation including pin mapping, cell types, instruction opcodes, and IDCODE; board-level test software uses BSDL files to automatically generate test patterns

Board-Level Test Applications:

• Interconnect Testing: EXTEST instruction drives known patterns from one chip's output cells and captures them at another chip's input cells to verify PCB trace connectivity; detects opens, shorts, and stuck-at faults on board-level interconnects without bed-of-nails fixtures
• Cluster Testing: groups of connected devices are tested simultaneously by configuring drivers and receivers across the boundary scan chain; sophisticated automatic test pattern generation (ATPG) tools create optimized pattern sets that maximize fault coverage
• In-System Programming (ISP): JTAG provides the data path for programming FPGAs, CPLDs, and flash memories on assembled boards; the same TAP port used for test serves as the programming interface, eliminating the need for separate programming fixtures
• Debug Access: ARM CoreSight, RISC-V debug modules, and other on-chip debug architectures use JTAG as the physical transport for breakpoint setting, register read/write, and memory access during software development and field diagnostics

Boundary scan and JTAG remain the universal board-level test and debug infrastructure — a 35-year-old standard that continues to evolve (IEEE 1149.7 reduced pin count, IEEE 1687 for internal access) while providing the foundational test access mechanism that enables manufacturing, programming, and diagnostics of every modern electronic system.