Bus protocol defines how initiators, targets and interconnect transfer addresses, data, control, responses and ordering inside a chip. Interconnect architecture determines whether processors, accelerators, memory and peripherals meet bandwidth, latency, coherency, isolation and power goals. SoCs evolved from shared buses such as AHB, through crossbars around AXI, toward rings and packet-switched networks-on-chip as endpoint count and concurrency grew. A production specification names the hardware and software boundary, clock and reset domains, address map, data widths, endianness, ordering and coherency, interrupt and error behavior, power states, security domains, performance targets, configuration discovery, lifecycle owner, and verification evidence. Marketing names and nominal link rates are insufficient without exact revision, mode, topology, payload, and environmental conditions. Specify topology, transaction model, channels, widths, clocks, arbitration, bursts, IDs, ordering, coherency, QoS, backpressure, errors, security, power states and verification.
Architecture, protocol behavior, and system integration. Shared bus arbitrates one path, crossbar connects several masters/slaves concurrently, ring forwards transactions around nodes, mesh NoC packetizes traffic through routers and coherent fabrics add directory/snoop semantics. Initiators issue transactions, interconnect decodes and routes, arbiters grant constrained resources, flow control buffers congestion, targets respond, and ordering points ensure architectural visibility. AMBA AHB/AXI/ACE/CHI, TileLink, Wishbone, Avalon, proprietary coherent fabrics and general NoCs balance openness, ecosystem, coherency and scale. A modern embedded system spans processor and accelerator IP, memory hierarchy, on-chip interconnect, peripheral controllers, analog and RF interfaces, clock/reset/power management, boot and firmware, board devices, operating-system discovery and drivers, diagnostics, update infrastructure, and application policy. Data, control, timing, trust, and power paths cross several abstraction levels. Evaluation combines functional correctness with bandwidth and payload efficiency, p50 and tail latency, jitter, outstanding depth, utilization, arbitration fairness, interrupt rate, CPU overhead, memory traffic, error and retry rate, power, thermal behavior, area, firmware footprint, startup time, recovery, interoperability, reliability, security, and total cost. Measurements state workload, clocks, voltages, formats, traffic mix, software, and instrumentation.
Implementation, physical design, and failure modes. Model traffic, choose topology, avoid deadlock classes, size links/buffers, define virtual channels, QoS/firewalls, bridge legacy protocols, insert CDC and register stages, instrument counters and verify end-to-end ordering. Wires dominate area/power at scale; crossbars grow poorly, rings have distance latency, meshes add routers/hops. Physical floorplan, congestion, clocks and voltage islands shape logical topology. Starvation, head-of-line blocking, cyclic dependencies, livelock, ordering breach, snoop race, address overlap, security bypass and power-domain isolation cause system failure. Implementation uses versioned interface specifications, register descriptions, generated headers where appropriate, typed driver APIs, clear ownership, bounded waits, idempotent initialization, capability discovery, defensive parsing, timeouts, error injection, telemetry, and safe fallback. Hardware and firmware agree on reset values, write side effects, ordering, cache maintenance, DMA ownership, interrupt acknowledgment, and power transitions. Physical results depend on standard-cell and memory libraries, analog/RF macros, PHYs, clock trees, voltage islands, level shifters, package pins, signal and power integrity, board routing, external components, thermal limits, process variation and test coverage. A protocol block that passes RTL simulation can still fail timing, CDC, analog compliance, EMI, or system integration. Common failures include reset races, clock-domain crossings, metastability, stale descriptors, dropped interrupts, cache incoherence, address aliasing, ordering violations, bus deadlock, DMA use-after-free, malformed firmware data, incompatible revisions, power-state loss, timeout storms, partial updates, security rollback and observability gaps. A working nominal demo does not establish corner correctness.
Verification, security, and lifecycle controls. Use traffic generators, protocol VIP, formal deadlock/order/connectivity properties, congestion stress, fairness, errors, coherency litmus tests, CDC/reset and post-layout performance. Bisection/payload bandwidth, hop and tail latency, utilization, fairness, buffer occupancy, blocking, power/bit, area, frequency, ordering and error matter. Address firewalls, privilege/security attributes, debug paths, DMA domains, coherency ownership and third-party IP trust require review. Verification combines lint, CDC/RDC, assertions, formal properties, protocol VIP, constrained-random simulation, emulation or FPGA prototypes, firmware unit and integration tests, compliance suites, interoperability matrices, performance and power measurement, fault injection, security review, silicon bring-up, characterization, production test, update/rollback drills, and long-duration stress. Requirements, IP and license versions, RTL, register maps, firmware, boot artifacts, device descriptions, drivers, compiler and OS, validation vectors, timing and power signoff, package/board revisions, fuse policy, manufacturing test, errata, field telemetry, update keys, approvals, incidents and deprecation remain linked. Compatibility rules span hardware generations that cannot be patched physically. Owners define root of trust, secure and measured boot, debug authorization, key and fuse handling, signed updates, anti-rollback, least privilege, DMA isolation, memory protection, data classification, radio and safety compliance, vulnerability response, support lifetime, supplier provenance, export/regional obligations, and auditable release authority.
| Interconnect | Topology/model | Concurrency | Coherency option | Best fit |
|---|---|---|---|---|
| AHB | Shared/pipelined bus | Limited | No native full coherence | Small SoCs/legacy |
| AXI | Channels plus crossbar/NoC | High outstanding | ACE extension | General SoCs |
| CHI | Packetized coherent fabric | High/scalable | Native coherent protocol | Many-core ARM systems |
| TileLink | Open parameterized links | Configurable | Cached coherent variants | RISC-V/open designs |
| Ring | Ordered circular path | Moderate | Design-specific | Mid-scale coherent systems |
| Mesh NoC | Packet routers/links | High distributed | Protocol overlay | Large heterogeneous SoCs |
<svg viewBox="0 0 760 470" xmlns="http://www.w3.org/2000/svg" font-family="Segoe UI,Arial,sans-serif"><rect width="760" height="470" fill="#0d1117"/><defs><marker id="ab" markerWidth="8" markerHeight="8" refX="6.5" refY="3" orient="auto"><path d="M0,0 L7,3 L0,6 Z" fill="#60a5fa"/></marker><marker id="ag" markerWidth="8" markerHeight="8" refX="6.5" refY="3" orient="auto"><path d="M0,0 L7,3 L0,6 Z" fill="#34d399"/></marker><marker id="am" markerWidth="8" markerHeight="8" refX="6.5" refY="3" orient="auto"><path d="M0,0 L7,3 L0,6 Z" fill="#c4b5fd"/></marker><marker id="ah" markerWidth="8" markerHeight="8" refX="6.5" refY="3" orient="auto"><path d="M0,0 L7,3 L0,6 Z" fill="#8b949e"/></marker></defs><text x="20" y="30" fill="#e6edf3" font-size="19" font-weight="700">On-chip interconnect: from a shared bus to AMBA AXI and beyond</text><text x="20" y="50" fill="#8b949e" font-size="12.5">As masters multiply, topology evolves bus → crossbar → NoC, while protocols like AXI pipeline addresses, data and responses.</text><rect x="20" y="66" width="226" height="298" rx="7" fill="#0c141d" stroke="#30363d"/><text x="32" y="87" fill="#e6edf3" font-size="13.5" font-weight="600">Topology evolution</text><rect x="267" y="66" width="226" height="298" rx="7" fill="#0c141d" stroke="#30363d"/><text x="279" y="87" fill="#e6edf3" font-size="13.5" font-weight="600">AXI: five channels</text><rect x="514" y="66" width="226" height="298" rx="7" fill="#0c141d" stroke="#30363d"/><text x="526" y="87" fill="#e6edf3" font-size="13.5" font-weight="600">Bursts & outstanding</text><text x="32" y="108" fill="#fbbf24" font-size="9.5" font-weight="700">shared bus</text><line x1="44" y1="128" x2="224" y2="128" stroke="#fbbf24" stroke-width="2.4"/><rect x="93" y="104" width="18" height="13" rx="2" fill="#12233a" stroke="#60a5fa" stroke-width="1"/><text x="102" y="114" fill="#60a5fa" font-size="7" text-anchor="middle">M</text><line x1="102" y1="117" x2="102" y2="128" stroke="#30475f" stroke-width="1"/><rect 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stroke="#30475f" stroke-width="1"/><circle cx="224" cy="128" r="7" fill="#3a2a17" stroke="#fbbf24" stroke-width="1"/><text x="224" y="130.5" fill="#fbbf24" font-size="6.5" text-anchor="middle">arb</text><text x="32" y="176" fill="#60a5fa" font-size="9.5" font-weight="700">crossbar</text><line x1="60" y1="200" x2="118" y2="200" stroke="#30475f" stroke-width="1.3"/><line x1="60" y1="218" x2="118" y2="218" stroke="#30475f" stroke-width="1.3"/><line x1="60" y1="236" x2="118" y2="236" stroke="#30475f" stroke-width="1.3"/><line x1="68" y1="194" x2="68" y2="242" stroke="#30475f" stroke-width="1.3"/><circle cx="68" cy="200" r="2.3" fill="#60a5fa"/><circle cx="68" cy="218" r="2.3" fill="#60a5fa"/><circle cx="68" cy="236" r="2.3" fill="#60a5fa"/><line x1="86" y1="194" x2="86" y2="242" stroke="#30475f" stroke-width="1.3"/><circle cx="86" cy="200" r="2.3" fill="#60a5fa"/><circle cx="86" cy="218" r="2.3" fill="#60a5fa"/><circle cx="86" cy="236" r="2.3" fill="#60a5fa"/><line x1="104" y1="194" x2="104" y2="242" stroke="#30475f" stroke-width="1.3"/><circle cx="104" cy="200" r="2.3" fill="#60a5fa"/><circle cx="104" cy="218" r="2.3" fill="#60a5fa"/><circle cx="104" cy="236" r="2.3" fill="#60a5fa"/><text x="126" y="218" fill="#8b949e" font-size="8">any-to-any,</text><text x="126" y="229" fill="#8b949e" font-size="8">wires grow N²</text><text x="32" y="258" fill="#c4b5fd" font-size="9.5" font-weight="700">NoC mesh</text><line x1="70" y1="272" x2="88" y2="272" stroke="#30475f" stroke-width="1.4"/><line x1="64" y1="278" x2="64" y2="296" stroke="#30475f" stroke-width="1.4"/><line x1="100" y1="272" x2="118" y2="272" stroke="#30475f" stroke-width="1.4"/><line x1="94" y1="278" x2="94" y2="296" stroke="#30475f" stroke-width="1.4"/><line x1="124" y1="278" x2="124" y2="296" stroke="#30475f" stroke-width="1.4"/><line x1="70" y1="302" x2="88" y2="302" stroke="#30475f" stroke-width="1.4"/><line x1="100" y1="302" x2="118" y2="302" stroke="#30475f" stroke-width="1.4"/><rect x="58" y="266" width="12" height="12" rx="2" fill="#241d33" stroke="#c4b5fd" stroke-width="1"/><rect x="88" y="266" width="12" height="12" rx="2" fill="#241d33" stroke="#c4b5fd" stroke-width="1"/><rect x="118" y="266" width="12" height="12" rx="2" fill="#241d33" stroke="#c4b5fd" stroke-width="1"/><rect x="58" y="296" width="12" height="12" rx="2" fill="#241d33" stroke="#c4b5fd" stroke-width="1"/><rect x="88" y="296" width="12" height="12" rx="2" fill="#241d33" stroke="#c4b5fd" stroke-width="1"/><rect x="118" y="296" width="12" height="12" rx="2" fill="#241d33" stroke="#c4b5fd" stroke-width="1"/><text x="154" y="302" fill="#8b949e" font-size="8">routed,</text><text x="154" y="313" fill="#8b949e" font-size="8">scales best</text><line x1="224" y1="138" x2="224" y2="242" stroke="#8b949e" stroke-width="0.8" stroke-dasharray="2 3"/><text x="226" y="216" fill="#8b949e" font-size="7.6" transform="rotate(90 226 216)">more endpoints</text><rect x="283" y="124" width="40" height="118" rx="5" fill="#12233a" stroke="#60a5fa" stroke-width="1.2"/><text x="303" y="180" fill="#93c5fd" font-size="9" text-anchor="middle" font-weight="700" transform="rotate(-90 303 184)">Master</text><rect x="447" y="124" width="40" height="118" rx="5" fill="#153524" stroke="#34d399" stroke-width="1.2"/><text x="467" y="184" fill="#6ee7b7" font-size="9" text-anchor="middle" font-weight="700" transform="rotate(-90 467 184)">Slave</text><line x1="323" y1="138" x2="445" y2="138" stroke="#60a5fa" stroke-width="1.6" marker-end="url(#ab)"/><text x="329" y="135" fill="#60a5fa" font-size="8.4" font-weight="700">AW</text><text x="349" y="135" fill="#8b949e" font-size="7.6">write addr</text><line x1="323" y1="160" x2="445" y2="160" stroke="#60a5fa" stroke-width="1.6" marker-end="url(#ab)"/><text x="329" y="157" fill="#60a5fa" font-size="8.4" font-weight="700">W</text><text x="349" y="157" fill="#8b949e" font-size="7.6">write data</text><line x1="447" y1="182" x2="325" y2="182" stroke="#34d399" stroke-width="1.6" marker-end="url(#ag)"/><text x="329" y="179" fill="#34d399" font-size="8.4" font-weight="700">B</text><text x="349" y="179" fill="#8b949e" font-size="7.6">write resp</text><line x1="323" y1="204" x2="445" y2="204" stroke="#c4b5fd" stroke-width="1.6" marker-end="url(#am)"/><text x="329" y="201" fill="#c4b5fd" font-size="8.4" font-weight="700">AR</text><text x="349" y="201" fill="#8b949e" font-size="7.6">read addr</text><line x1="447" y1="226" x2="325" y2="226" stroke="#34d399" stroke-width="1.6" marker-end="url(#ag)"/><text x="329" y="223" fill="#34d399" font-size="8.4" font-weight="700">R</text><text x="349" y="223" fill="#8b949e" font-size="7.6">read data</text><text x="267" y="262" fill="#8b949e" font-size="8.4">3 write + 2 read channels run independently.</text><text x="283" y="276" fill="#e6edf3" font-size="9" font-weight="600">VALID / READY handshake</text><text x="283" y="296" fill="#60a5fa" font-size="7.6">VALID</text><path d="M317,298 L353,298 L353,288 L433,288 L433,298 L463,298" fill="none" stroke="#60a5fa" stroke-width="1.4"/><text x="283" y="320" fill="#34d399" font-size="7.6">READY</text><path d="M317,322 L378,322 L378,312 L433,312 L433,322 L463,322" fill="none" stroke="#34d399" stroke-width="1.4"/><rect x="378" y="284" width="55" height="42" fill="#fbbf24" opacity="0.12"/><line x1="405" y1="284" x2="405" y2="330" stroke="#fbbf24" stroke-width="0.8" stroke-dasharray="2 2"/><text x="405" y="338" fill="#fbbf24" font-size="7.6" text-anchor="middle">transfer when both high</text><text x="526" y="108" fill="#8b949e" font-size="9.2">one address, many data beats (burst)</text><rect x="536" y="128" width="34" height="18" rx="3" fill="#12233a" stroke="#60a5fa" stroke-width="1.1"/><text x="553" y="140" fill="#93c5fd" font-size="7.8" text-anchor="middle" font-weight="700">AW</text><text x="553" y="158" fill="#8b949e" font-size="7" text-anchor="middle">addr</text><rect x="588" y="128" width="32" height="18" rx="3" fill="#153524" stroke="#34d399" stroke-width="1.1"/><text x="604" y="140" fill="#6ee7b7" font-size="7.6" text-anchor="middle">D0</text><line x1="620" y1="137" x2="626" y2="137" stroke="#8b949e" stroke-width="0.9" marker-end="url(#ah)"/><rect x="626" y="128" width="32" height="18" rx="3" fill="#153524" stroke="#34d399" stroke-width="1.1"/><text x="642" y="140" fill="#6ee7b7" font-size="7.6" text-anchor="middle">D1</text><line x1="658" y1="137" x2="664" y2="137" stroke="#8b949e" stroke-width="0.9" marker-end="url(#ah)"/><rect x="664" y="128" width="32" height="18" rx="3" fill="#153524" stroke="#34d399" stroke-width="1.1"/><text x="680" y="140" fill="#6ee7b7" font-size="7.6" text-anchor="middle">D2</text><line x1="696" y1="137" x2="702" y2="137" stroke="#8b949e" stroke-width="0.9" marker-end="url(#ah)"/><rect x="702" y="128" width="32" height="18" rx="3" fill="#153524" stroke="#34d399" stroke-width="1.1"/><text x="718" y="140" fill="#6ee7b7" font-size="7.6" text-anchor="middle">D3</text><line x1="570" y1="137" x2="588" y2="137" stroke="#8b949e" stroke-width="0.9" marker-end="url(#ah)"/><text x="656" y="158" fill="#8b949e" font-size="7" text-anchor="middle">4-beat data burst</text><text x="526" y="178" fill="#e6edf3" font-size="9.5" font-weight="600">Outstanding transactions</text><rect x="532" y="186" width="120" height="12" rx="2" fill="#1e3a5f" stroke="#60a5fa" stroke-width="0.9"/><text x="536" y="195" fill="#93c5fd" font-size="7.4">ID=0 addr → data</text><rect x="574" y="202" width="120" height="12" rx="2" fill="#241d33" stroke="#c4b5fd" stroke-width="0.9"/><text x="578" y="211" fill="#c4b5fd" font-size="7.4">ID=1 addr → data</text><text x="526" y="230" fill="#8b949e" font-size="8.2">IDs let requests overlap and return</text><text x="526" y="241" fill="#8b949e" font-size="8.2">out of order — hides memory latency.</text><text x="526" y="264" fill="#e6edf3" font-size="9.5" font-weight="600">What decides the fit</text><circle cx="534" cy="275" r="2.2" fill="#fbbf24"/><text x="542" y="278" fill="#cdd9e5" font-size="8.6">ordering & IDs</text><circle cx="534" cy="288" r="2.2" fill="#fbbf24"/><text x="542" y="291" fill="#cdd9e5" font-size="8.6">QoS / priority</text><circle cx="534" cy="301" r="2.2" fill="#fbbf24"/><text x="542" y="304" fill="#cdd9e5" font-size="8.6">coherency (CHI, ACE)</text><circle cx="534" cy="314" r="2.2" fill="#fbbf24"/><text x="542" y="317" fill="#cdd9e5" font-size="8.6">power & wires</text><rect x="20" y="384" width="226" height="70" rx="7" fill="#111a24" stroke="#30363d"/><text x="32" y="403" fill="#e6edf3" font-size="12.5" font-weight="700">Why topology evolves</text><text x="32" y="420" fill="#cdd9e5" font-size="10">A shared bus is cheap but only one master</text><text x="32" y="433" fill="#cdd9e5" font-size="10">talks at a time. Crossbars add any-to-any</text><text x="32" y="446" fill="#cdd9e5" font-size="10">paths; a NoC routes packets so hundreds of</text><text x="32" y="459" fill="#cdd9e5" font-size="10">tiles scale.</text><rect x="267" y="384" width="226" height="70" rx="7" fill="#111a24" stroke="#30363d"/><text x="279" y="403" fill="#e6edf3" font-size="12.5" font-weight="700">AXI in one line</text><text x="279" y="420" fill="#cdd9e5" font-size="10">Separate address, data and response channels</text><text x="279" y="433" fill="#cdd9e5" font-size="10">move with a simple VALID/READY handshake, so</text><text x="279" y="446" fill="#cdd9e5" font-size="10">reads and writes pipeline instead of stalling.</text><rect x="514" y="384" width="226" height="70" rx="7" fill="#111a24" stroke="#30363d"/><text x="526" y="403" fill="#e6edf3" font-size="12.5" font-weight="700">Bursts and IDs</text><text x="526" y="420" fill="#cdd9e5" font-size="10">Send one address then a burst of data beats,</text><text x="526" y="433" fill="#cdd9e5" font-size="10">and tag transactions with IDs so many stay</text><text x="526" y="446" fill="#cdd9e5" font-size="10">outstanding at once. That is how bandwidth is</text><text x="526" y="459" fill="#cdd9e5" font-size="10">won.</text></svg>
Selection and practical application. Use simple buses for small MCUs, AXI crossbars for moderate SoCs, coherent CHI/TileLink-style fabrics for shared caches and NoCs for many heterogeneous endpoints. MCUs, application processors, accelerators, networking, automotive, FPGA and chiplet systems use bus/interconnect protocols. Interconnect design links architecture traffic, IP protocols, coherence, memory, floorplan, clocks/power, security, firmware QoS and verification. The useful design boundary is the complete hardware-software system. Optimizing an IP block, bus, driver, codec, radio, controller or firmware stage can move the bottleneck or weaken correctness, timing, power, safety, security, recoverability and manufacturability elsewhere, so qualification is end to end. A production specification names the hardware and software boundary, clock and reset domains, address map, data widths, endianness, ordering and coherency, interrupt and error behavior, power states, security domains, performance targets, configuration discovery, lifecycle owner, and verification evidence. Marketing names and nominal link rates are insufficient without exact revision, mode, topology, payload, and environmental conditions. Evaluation combines functional correctness with bandwidth and payload efficiency, p50 and tail latency, jitter, outstanding depth, utilization, arbitration fairness, interrupt rate, CPU overhead, memory traffic, error and retry rate, power, thermal behavior, area, firmware footprint, startup time, recovery, interoperability, reliability, security, and total cost. Measurements state workload, clocks, voltages, formats, traffic mix, software, and instrumentation. CFS connects this topic to semiconductor architecture, implementation, verification, manufacturing, packaging, test, and deployed AI-system tradeoffs across the platform.
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